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| author | Bill Traynor <wmat@riscv.org> | 2023-01-13 14:45:52 -0500 |
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| committer | Bill Traynor <wmat@riscv.org> | 2023-01-13 14:45:52 -0500 |
| commit | 6e7207da15da0f4bdf51e8bc34569cb3c3c89279 (patch) | |
| tree | 634bf97aad66ab7b0b8abd93d2abb6ee764db618 /src/a-st-ext.adoc | |
| parent | 4009aad3c7444024abc10b5118ebbdf1cbd02454 (diff) | |
| download | riscv-isa-manual-6e7207da15da0f4bdf51e8bc34569cb3c3c89279.zip riscv-isa-manual-6e7207da15da0f4bdf51e8bc34569cb3c3c89279.tar.gz riscv-isa-manual-6e7207da15da0f4bdf51e8bc34569cb3c3c89279.tar.bz2 | |
Changing Cite to cite.
Changing Cite to cite.
Diffstat (limited to 'src/a-st-ext.adoc')
| -rw-r--r-- | src/a-st-ext.adoc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/a-st-ext.adoc b/src/a-st-ext.adoc index 7aaba81..5429026 100644 --- a/src/a-st-ext.adoc +++ b/src/a-st-ext.adoc @@ -9,7 +9,7 @@ load-reserved/store-conditional instructions and atomic fetch-and-op memory instructions. Both types of atomic instruction support various memory consistency orderings including unordered, acquire, release, and sequentially consistent semantics. These instructions allow RISC-V to -support the RCsc memory consistency model. Cite:[Gharachorloo90memoryconsistency] +support the RCsc memory consistency model. cite:[Gharachorloo90memoryconsistency] [NOTE] ==== @@ -26,7 +26,7 @@ space is divided by the execution environment into memory and I/O domains, and the FENCE instruction provides options to order accesses to one or both of these two address domains. -To provide more efficient support for release consistency Cite:[Gharachorloo90memoryconsistency], each atomic +To provide more efficient support for release consistency cite:[Gharachorloo90memoryconsistency], each atomic instruction has two bits, _aq_ and _rl_, used to specify additional memory ordering constraints as viewed by other RISC-V harts. The bits order accesses to one of the two address domains, memory or I/O, |