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| author | Ibrahim Abu Kharmeh <abukharmeh@gmail.com> | 2022-02-17 23:43:47 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-17 15:43:47 -0800 |
| commit | 3863e4147c6fa81d72912f65d010d3010c70b01c (patch) | |
| tree | 493dbda59710f2f45a315dccfcb508f556282e25 /marchid.md | |
| parent | 69c3cd6323381827f3199d0f19ad0cb72ef97155 (diff) | |
| download | riscv-isa-manual-3863e4147c6fa81d72912f65d010d3010c70b01c.zip riscv-isa-manual-3863e4147c6fa81d72912f65d010d3010c70b01c.tar.gz riscv-isa-manual-3863e4147c6fa81d72912f65d010d3010c70b01c.tar.bz2 | |
Adds CV32E41P to MARCHID (#818)
Adds [CV32E41P ]https://github.com/openhwgroup/cv32e41p to the MARCHID list. The core started its life as a fork of the CV32E40P core to implement the official RISC-V [Zfinx](https://github.com/riscv/riscv-zfinx/blob/main/zfinx-spec-20210511-0.41.pdf) and [Zce](https://github.com/riscv/riscv-code-size-reduction/releases/tag/V0.50.1-TOOLCHAIN-DEV) ISA extensions.
Closes https://github.com/openhwgroup/cv32e41p/issues/7
Diffstat (limited to 'marchid.md')
| -rw-r--r-- | marchid.md | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -45,3 +45,4 @@ Steel Core | Rafael Calcada | [Rafael Calcada](mailto:rafael XiangShan | ICT, CAS | [XiangShan Team](mailto:xiangshan-all@ict.ac.cn) | 25 | https://github.com/OpenXiangShan/XiangShan Hummingbirdv2 E203 | Nuclei System Technology | [Can Hu](mailto:canhu@nucleisys.com), Nuclei System Technology | 26 | https://github.com/riscv-mcu/e203_hbirdv2 Hazard3 | Luke Wren | [Luke Wren](mailto:wren6991@gmail.com) | 27 | https://github.com/wren6991/hazard3 +CV32E41P | OpenHW Group | [Mark Hill](mailto:mark.hill@huawei.com), OpenHW Group | 28 | https://github.com/openhwgroup/cv32e41p |