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| author | Andrew Waterman <andrew@sifive.com> | 2018-10-04 15:18:27 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-10-04 15:18:27 -0700 |
| commit | 4bf712347e6fede7c9119faed2d66b9bd9741a42 (patch) | |
| tree | 95c6a62340fced8e9b987b16cbb38c7acb12c34a /marchid.md | |
| parent | 71597dd3ad89a2262d240680793586a8ebdec308 (diff) | |
| download | riscv-isa-manual-4bf712347e6fede7c9119faed2d66b9bd9741a42.zip riscv-isa-manual-4bf712347e6fede7c9119faed2d66b9bd9741a42.tar.gz riscv-isa-manual-4bf712347e6fede7c9119faed2d66b9bd9741a42.tar.bz2 | |
Allocate Spike marchid
Diffstat (limited to 'marchid.md')
| -rw-r--r-- | marchid.md | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -19,3 +19,4 @@ ID. Project Name | Maintainers | Point of Contact | Architecture ID | Project URL -------------|-------------------------------|---------------------------------------------------------|-----------------|--------------------------------------------------- Rocket | SiFive, UC Berkeley | [Andrew Waterman](mailto:andrew@sifive.com), SiFive | 1 | https://github.com/freechipsproject/rocket-chip +Spike | SiFive, UC Berkeley | [Andrew Waterman](mailto:andrew@sifive.com), SiFive | 5 | https://github.com/riscv/riscv-isa-sim |