Merge pull request #860 from riscv/rv32e-rv64e-ratification

Draft of RV32E and RV64E chapter for ratification.

1 files changed, 29 insertions, 40 deletions

diff --git a/src/rv32e.tex b/src/rv32e.tex
index 92e79c5..bf770f1 100644
--- a/src/rv32e.tex
+++ b/src/rv32e.tex
@@ -1,58 +1,47 @@
-\chapter{RV32E Base Integer Instruction Set, Version 1.9}
+\chapter{RV32E and RV64E Base Integer Instruction Sets, Version 1.95}
 \label{rv32e}
 
-This chapter describes a draft proposal for the RV32E base integer
-instruction set, which is a reduced version of RV32I designed for
-embedded systems.  The only change is to reduce the number of integer
-registers to 16.  This chapter only outlines the differences between
-RV32E and RV32I, and so should be read after Chapter~\ref{rv32}.
+This chapter describes a proposal for the RV32E and RV64E base integer
+instruction sets, designed for microcontrollers in embedded systems.
+RV32E and RV64E are reduced versions of RV32I and RV64I, respectively:
+the only change is to reduce the number of integer registers to 16.
+This chapter only outlines the differences between RV32E/RV64E and
+RV32I/RV64I, and so should be read after Chapters~\ref{rv32} and
+\ref{rv64}.
 
 \begin{commentary}
 RV32E was designed to provide an even smaller base core for embedded
-microcontrollers.  Although we had mentioned this possibility in
-version 2.0 of this document, we initially resisted defining this
-subset. However, given the demand for the smallest possible 32-bit
-microcontroller, and in the interests of preempting fragmentation in
-this space, we have now defined RV32E as a fourth standard base ISA in
-addition to RV32I, RV64I, and RV128I.  There is also interest in
-defining an RV64E to reduce context state for highly threaded 64-bit
-processors.
+microcontrollers.  There is also interest in RV64E for
+microcontrollers within large SoC designs, and to reduce context state
+for highly threaded 64-bit processors.
+
+RV32E and RV64E can be combined with all current standard extensions.
 \end{commentary}
 
-\section{RV32E Programmers' Model}
+\section{RV32E and RV64E Programmers' Model}
 
-RV32E reduces the integer register count to 16 general-purpose
-registers, ({\tt x0}--{\tt x15}), where {\tt x0} is a dedicated zero
-register.
+RV32E and RV64E reduce the integer register count to 16
+general-purpose registers, ({\tt x0}--{\tt x15}), where {\tt x0} is a
+dedicated zero register.
 
 \begin{commentary}
-We have found that in the small RV32I core designs, the upper 16
-registers consume around one quarter of the total area of the core
+We have found that in the small RV32I core implementations, the upper
+16 registers consume around one quarter of the total area of the core
 excluding memories, thus their removal saves around 25\% core area
 with a corresponding core power reduction.
 \end{commentary}
 
-\begin{commentary}
-This change requires a different calling convention and ABI.  In
-particular, RV32E is only used with a soft-float calling convention.
-A new embedded ABI is under consideration that would work across RV32E
-and RV32I.
-\end{commentary}
-
-\section{RV32E Instruction Set}
+\section{RV32E and RV64E Instruction Set Encoding}
 
-RV32E uses the same instruction-set encoding as RV32I, except that
-only registers {\tt x0}--{\tt x15} are provided.  Any future standard
-extensions will not make use of the instruction bits freed up by the
-reduced register-specifier fields and so these are designated for
-custom extensions.
+RV32E and RV64E use the same instruction-set encoding as RV32I and
+RV64I respectively, except that only registers {\tt x0}--{\tt x15} are
+provided.  All encodings specifying the other registers {\tt x16}--{\tt
+  x31} are reserved.
 
 \begin{commentary}
-RV32E can be combined with all current standard extensions. Defining the F, D,
-and Q extensions as having a 16-entry floating point register file when
-combined with RV32E was considered but decided against. To support
-systems with reduced floating-point register state, we intend to
-define a ``Zfinx'' extension that makes floating-point computations use the
-integer registers, removing the floating-point loads, stores, and moves between
-floating point and integer registers.
+The previous draft of this chapter made all encodings using the {\tt
+  x16}--{\tt x31} registers available as custom.  This version takes a
+more conservative approach, making these reserved so that they can be
+allocated between custom space or new standard encodings at a later
+date.
 \end{commentary}