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| author | Andrew Waterman <andrew@sifive.com> | 2024-01-29 23:15:22 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-01-29 23:15:22 -0800 |
| commit | 8e53b52e9e8f2089af699fd23f168e201141c8e3 (patch) | |
| tree | db5ae35a83c42d4490f78a26175a8ec2946ff57f | |
| parent | 33aae57085fd8622dee6dae9e9c5912dc1bd6d1c (diff) | |
| download | riscv-isa-manual-8e53b52e9e8f2089af699fd23f168e201141c8e3.zip riscv-isa-manual-8e53b52e9e8f2089af699fd23f168e201141c8e3.tar.gz riscv-isa-manual-8e53b52e9e8f2089af699fd23f168e201141c8e3.tar.bz2 | |
Add changelog entry for #1116
| -rw-r--r-- | src/priv-preface.adoc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc index c6b4aec..2a82c39 100644 --- a/src/priv-preface.adoc +++ b/src/priv-preface.adoc @@ -58,6 +58,7 @@ in `menvcfg` and `henvcfg`. * Clarified ordering rules for hardware A/D bit updates. * Clarified that, for a given exception cause, `__x__tval` might sometimes be set to a nonzero value but sometimes not. +* Clarified exception behavior of unimplemented or inaccessible CSRs. * Defined hardware error and software check exception codes. [.big]*_Preface to Version 20211203_* |