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| author | Andrew Waterman <andrew@sifive.com> | 2024-01-29 17:47:00 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-01-30 15:56:14 -0800 |
| commit | 7465a80f3d4ba52c015faf301a8179452f2adc96 (patch) | |
| tree | 59081c23aa1dc700cfd7b6bf2a071c08ea105833 | |
| parent | d88c7d1931c6a5987894013f514429b82877a027 (diff) | |
| download | riscv-isa-manual-7465a80f3d4ba52c015faf301a8179452f2adc96.zip riscv-isa-manual-7465a80f3d4ba52c015faf301a8179452f2adc96.tar.gz riscv-isa-manual-7465a80f3d4ba52c015faf301a8179452f2adc96.tar.bz2 | |
Add menvcfg.ADUE
| -rw-r--r-- | src/images/bytefield/menvcfgreg.adoc | 10 | ||||
| -rw-r--r-- | src/machine.adoc | 19 |
2 files changed, 25 insertions, 4 deletions
diff --git a/src/images/bytefield/menvcfgreg.adoc b/src/images/bytefield/menvcfgreg.adoc index 74de88b..979634a 100644 --- a/src/images/bytefield/menvcfgreg.adoc +++ b/src/images/bytefield/menvcfgreg.adoc @@ -3,12 +3,13 @@ (defattrs :plain [:plain {:font-family "M+ 1p Fallback"}]) (def row-height 45) (def row-header-fn nil) -(def boxes-per-row 32) -(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "1" "3" "4" "5" "6" "" "7" "" "8" "" "" "" "" "" "31" "32" "" "33" "34" "" "" "" "" "" "" "61" "" "62" "" "63"])}) +(def boxes-per-row 33) +(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "1" "3" "4" "5" "6" "" "7" "" "8" "" "" "" "" "" "31" "32" "" "33" "34" "" "" "" "" "" "60" "" "61" "" "62" "" "63"])}) (draw-box "STCE" {:span 2}) (draw-box "PBMTE" {:span 2}) -(draw-box (text "WPRI" {:font-weight "bold"}) {:span 8}) +(draw-box "ADUE" {:span 2}) +(draw-box (text "WPRI" {:font-weight "bold"}) {:span 7}) (draw-box "PMM" {:span 3}) (draw-box (text "WPRI" {:font-weight "bold"}) {:span 7}) (draw-box "CBZE" {:span 2}) @@ -19,7 +20,8 @@ (draw-box "1" {:span 2 :borders {}}) (draw-box "1" {:span 2 :borders {}}) -(draw-box "28" {:span 8 :borders {}}) +(draw-box "1" {:span 2 :borders {}}) +(draw-box "27" {:span 7 :borders {}}) (draw-box "2" {:span 3 :borders {}}) (draw-box "24" {:span 7 :borders {}}) (draw-box "1" {:span 2 :borders {}}) diff --git a/src/machine.adoc b/src/machine.adoc index 5f70b22..c12ebda 100644 --- a/src/machine.adoc +++ b/src/machine.adoc @@ -2031,6 +2031,25 @@ with respect to the altered interpretation of page-table entries' PBMT fields. See <<hyp-mm-fences>> for additional synchronization requirements when the hypervisor extension is implemented. +If the Svadu extension is implemented, the ADUE bit controls whether hardware +updating of PTE A/D bits is enabled for S-mode and G-stage address +translations. +When ADUE=1, hardware updating of PTE A/D bits is enabled during S-mode +address translation, and the implementation behaves as though the Svade +extension were not implemented for S-mode address translation. +When the hypervisor extension is implemented, if ADUE=1, hardware updating of +PTE A/D bits is enabled during G-stage address translation, and the +implementation behaves as though the Svade extension were not implemented for +G-stage address translation. +When ADUE=0, the implementation behaves as though Svade were implemented for +S-mode and G-stage address translation. +If Svadu is not implemented, ADUE is read-only zero. +Furthermore, for implementations with the hypervisor extension, `henvcfg`.ADUE +is read-only zero if `menvcfg`.ADUE is zero. + +NOTE: The Svade extension requires page-fault exceptions be raised when PTE +A/D bits need be set, hence Svade is implemented when ADUE=0. + The definition of the STCE field will be furnished by the forthcoming Sstc extension. Its allocation within `menvcfg` may change prior to the ratification of that extension. |