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author | Andrew Waterman <andrew@sifive.com> | 2023-10-30 17:54:38 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2023-10-30 18:02:14 -0700 |
commit | 12dc920b44e4a54f70ac1a7ab07e9ccba80c8fd8 (patch) | |
tree | 0077eac9cba0a0c1921f49a26428afa42d8cd087 | |
parent | ea578803bfdedfdeb77f996062b7ad4c82369ba6 (diff) | |
download | riscv-isa-manual-12dc920b44e4a54f70ac1a7ab07e9ccba80c8fd8.zip riscv-isa-manual-12dc920b44e4a54f70ac1a7ab07e9ccba80c8fd8.tar.gz riscv-isa-manual-12dc920b44e4a54f70ac1a7ab07e9ccba80c8fd8.tar.bz2 |
Reserve interrupt 13 for Sscofpmf
Resolves #1127
Note, I only reserved the pattern in the various cause registers; I did not
update the various ip/ie registers. That work is left for whoever integrates
Sscofpmf into this document. Reserving the cause patterns has the same
architectural effect in the near term.
-rw-r--r-- | src/hypervisor.adoc | 5 | ||||
-rw-r--r-- | src/machine.adoc | 8 | ||||
-rw-r--r-- | src/priv-preface.adoc | 1 | ||||
-rw-r--r-- | src/supervisor.adoc | 8 |
4 files changed, 19 insertions, 3 deletions
diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc index 7f63f69..124afca 100644 --- a/src/hypervisor.adoc +++ b/src/hypervisor.adoc @@ -1755,11 +1755,14 @@ Virtual supervisor external interrupt + Machine external interrupt |1 + 1 + +1 + 1 |12 + -13-15 + +13 + +14-15 + ≥16 |Supervisor guest external interrupt + +_Reserved for counter-overflow interrupt_ + _Reserved_ + _Designated for platform use_ |0 + diff --git a/src/machine.adoc b/src/machine.adoc index 5c323d9..12bc039 100644 --- a/src/machine.adoc +++ b/src/machine.adoc @@ -1677,10 +1677,16 @@ Supervisor external interrupt + _Reserved_ + Machine external interrupt |1 + +1 + +1 + 1 -|12-15 + +|12 + +13 + +14-15 + ≥16 |_Reserved_ + +_Reserved for counter-overflow interrupt_ + +_Reserved_ + _Designated for platform use_ |0 + 0 + diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc index a300fbe..5509389 100644 --- a/src/priv-preface.adoc +++ b/src/priv-preface.adoc @@ -37,6 +37,7 @@ version 1.12: * Defined the `misa`.V field to reflect that the V extension has been implemented. * Defined the RV32-only `medelegh` and `hedelegh` CSRs. +* Reserved interrupt 13 for forthcoming counter-overflow interrupt extension. * Specified synchronization requirements when changing the PBMTE fields in `menvcfg` and `henvcfg`. * Clarified that "platform- or custom-use" interrupts are actually diff --git a/src/supervisor.adoc b/src/supervisor.adoc index a860ce5..16b74d3 100644 --- a/src/supervisor.adoc +++ b/src/supervisor.adoc @@ -425,6 +425,8 @@ include::images/bytefield/scausereg.edn[] 1 + 1 + 1 + +1 + +1 + 1 |0 + 1 + @@ -432,7 +434,9 @@ include::images/bytefield/scausereg.edn[] 5 + 6-8 + 9 + -10-15 + +10-12 + +13 + +14-15 + ≥16 |_Reserved_ + Supervisor software interrupt + @@ -441,6 +445,8 @@ Supervisor timer interrupt + _Reserved_ + Supervisor external interrupt + _Reserved_ + +_Reserved for counter-overflow interrupt_ + +_Reserved_ + _Designated for platform use_ |0 + |