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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2022-07-06 16:18:24 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-07-06 16:18:24 -0700 |
| commit | f983b86303235b13434522aa98927ee0633fa08a (patch) | |
| tree | a899d6332425d9eb50c652e26481b09d7c794253 | |
| parent | ca0a010494847c841660e92131b0add2593b2cf6 (diff) | |
| parent | cbbaa897f6ee583bccde30023fc0b5ce17c0504d (diff) | |
| download | riscv-isa-manual-f983b86303235b13434522aa98927ee0633fa08a.zip riscv-isa-manual-f983b86303235b13434522aa98927ee0633fa08a.tar.gz riscv-isa-manual-f983b86303235b13434522aa98927ee0633fa08a.tar.bz2 | |
Merge pull request #865 from riscv/counter-clarification
Clarify that time CSR one-tick constraint is not merely user-level
| -rw-r--r-- | src/counters.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/counters.tex b/src/counters.tex index ce0f02b..545804b 100644 --- a/src/counters.tex +++ b/src/counters.tex @@ -63,7 +63,7 @@ to read these CSRs. \end{commentary} For base ISAs with XLEN=32, the Zicntr extension enables the three -64-bit read-only user-level counters to be accessed in 32-bit pieces. +64-bit read-only counters to be accessed in 32-bit pieces. The RDCYCLE, RDTIME, and RDINSTRET pseudoinstructions provide the lower 32 bits, and the RDCYCLEH, RDTIMEH, and RDINSTRETH pseudoinstructions provide the upper 32 bits of the respective counters. @@ -165,7 +165,7 @@ wide variety of possible implementation platforms. The maximum error bound should be set based on the requirements of the platform. \end{commentary} -The real-time clocks of all harts in a single user application +The real-time clocks of all harts must be synchronized to within one tick of the real-time clock. \begin{commentary} |