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author | Andrew Waterman <andrew@sifive.com> | 2022-09-16 20:19:26 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-09-16 20:19:26 -0700 |
commit | c0db46f72a1cc409194bf7f11c09e69a387f16a0 (patch) | |
tree | f3b4fdb92be57c4090c32a91730aeab44a0db3ba | |
parent | 418a1b24ce0dd2039723f7356091c21e7f95f56d (diff) | |
download | riscv-isa-manual-c0db46f72a1cc409194bf7f11c09e69a387f16a0.zip riscv-isa-manual-c0db46f72a1cc409194bf7f11c09e69a387f16a0.tar.gz riscv-isa-manual-c0db46f72a1cc409194bf7f11c09e69a387f16a0.tar.bz2 |
Fix RVE non-normative comment
Not all extensions (e.g. hypervisor) are compatible with RV32E.
-rw-r--r-- | src/rv32e.tex | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/rv32e.tex b/src/rv32e.tex index bf770f1..7a61dcb 100644 --- a/src/rv32e.tex +++ b/src/rv32e.tex @@ -15,7 +15,8 @@ microcontrollers. There is also interest in RV64E for microcontrollers within large SoC designs, and to reduce context state for highly threaded 64-bit processors. -RV32E and RV64E can be combined with all current standard extensions. +Unless otherwise stated, standard extensions compatible with RV32I +and RV64I are also compatible with RV32E and RV64E, respectively. \end{commentary} \section{RV32E and RV64E Programmers' Model} |