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| author | Andrew Waterman <andrew@sifive.com> | 2022-09-20 20:47:33 -0700 |
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| committer | Andrew Waterman <andrew@sifive.com> | 2022-09-20 20:47:33 -0700 |
| commit | a37c1d2551cef57ca7d91b8e1c83730bbeb6d6d9 (patch) | |
| tree | dc8bea00932dfb1e43504911192fabe2a31f7e33 | |
| parent | 6599b4300f3694456c7f58c8f7c270ba4c5aab70 (diff) | |
| download | riscv-isa-manual-a37c1d2551cef57ca7d91b8e1c83730bbeb6d6d9.zip riscv-isa-manual-a37c1d2551cef57ca7d91b8e1c83730bbeb6d6d9.tar.gz riscv-isa-manual-a37c1d2551cef57ca7d91b8e1c83730bbeb6d6d9.tar.bz2 | |
Add Zihintntl draft warning
| -rw-r--r-- | src/zihintntl.tex | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/zihintntl.tex b/src/zihintntl.tex index f71c7ac..6b0be58 100644 --- a/src/zihintntl.tex +++ b/src/zihintntl.tex @@ -1,6 +1,9 @@ \chapter{``Zihintntl'' Non-Temporal Locality Hints, Version 0.2} \label{chap:zihintntl} +{\bf Warning! This draft specification may change before being +accepted as standard by RISC-V International.} + The NTL instructions are HINTs that indicate that the explicit memory accesses of the immediately subsequent instruction (henceforth ``target instruction'') exhibit poor temporal locality of reference. The NTL instructions do not change architectural state, nor do they alter the |