Renamed mbadbits to mtval (for "Trap Value") to be more generic name for register containing data related to the current trap.

3 files changed, 23 insertions, 23 deletions

diff --git a/src/machine.tex b/src/machine.tex
index 376581f..83051aa 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1692,19 +1692,19 @@ interrupt bit and scale the exception codes to index into a trap
 vector table.
 \end{commentary}
 
-\subsection{Machine Bad Bits ({\tt mbadbits}) Register}
+\subsection{Machine Bad Bits ({\tt mtval}) Register}
 
-The {\tt mbadbits} register is an XLEN-bit read-write register
-formatted as shown in Figure~\ref{mbadbitsreg}. When a hardware
+The {\tt mtval} register is an XLEN-bit read-write register
+formatted as shown in Figure~\ref{mtvalreg}. When a hardware
 breakpoint is triggered, or an instruction-fetch, load, or store
-address-misaligned, access, or page-fault exception occurs, {\tt mbadbits} is
+address-misaligned, access, or page-fault exception occurs, {\tt mtval} is
 written with the faulting effective address.  On an illegal instruction trap,
-{\tt mbadbits} is written with the first XLEN bits of the faulting
-instruction as described below.  {\tt mbadbits} is not modified for
+{\tt mtval} is written with the first XLEN bits of the faulting
+instruction as described below.  {\tt mtval} is not modified for
 other exceptions.
 
 \begin{commentary}
-  The {\tt mbadbits} register replaces the {\tt mbadaddr} register in
+  The {\tt mtval} register replaces the {\tt mbadaddr} register in
   the previous specification.  In addition to providing bad addresses,
   the register can now provide the bad instruction that triggered an
   illegal instruction trap (and may in future be used to return other
@@ -1713,7 +1713,7 @@ other exceptions.
   illegal instructions.
 \end{commentary}
 \begin{commentary}
-  When page-based virtual memory is enabled, {\tt mbadbits} is written with
+  When page-based virtual memory is enabled, {\tt mtval} is written with
   the faulting virtual address, even for physical-memory access exceptions.
   This design reduces datapath cost for most implementations, particularly
   those with hardware page-table walkers.
@@ -1725,7 +1725,7 @@ other exceptions.
 \begin{tabular}{@{}J}
 \instbitrange{XLEN-1}{0} \\
 \hline
-\multicolumn{1}{|c|}{\tt mbadbits} \\
+\multicolumn{1}{|c|}{\tt mtval} \\
 \hline
 XLEN \\
 \end{tabular}
@@ -1733,26 +1733,26 @@ XLEN \\
 }
 \vspace{-0.1in}
 \caption{Machine bad bits register.}
-\label{mbadbitsreg}
+\label{mtvalreg}
 \end{figure}
 
 For instruction-fetch access faults on RISC-V systems with
-variable-length instructions, {\tt mbadbits} will contain a pointer to
+variable-length instructions, {\tt mtval} will contain a pointer to
 the portion of the instruction that caused the fault while {\tt mepc}
 will point to the beginning of the instruction.
 
-The {\tt mbadbits} register can optionally also be used to return the
+The {\tt mtval} register can optionally also be used to return the
 faulting instruction bits on an illegal instruction exception ({\tt
   mepc} points to the faulting instruction in memory).
 
-If this feature is not provided, then {\tt mbadbits} is set to zero on
+If this feature is not provided, then {\tt mtval} is set to zero on
 an illegal instruction fault.
 
 If the feature is provided, after an illegal instruction trap, {\tt
-  mbadbits} will contain the entire faulting instruction provided the
+  mtval} will contain the entire faulting instruction provided the
 instruction is no longer than XLEN bits.  If the instruction is less
-than XLEN bits long, the upper bits of {\tt mbadbits} are cleared to
-zero. If the instruction is more than XLEN bits long, {\tt mbadbits}
+than XLEN bits long, the upper bits of {\tt mtval} are cleared to
+zero. If the instruction is more than XLEN bits long, {\tt mtval}
 will contain the first XLEN bits of the instruction.
 
 \begin{commentary}
@@ -1765,12 +1765,12 @@ will contain the first XLEN bits of the instruction.
   instruction memory, as might occur in a dynamic translation system.
 
   A requirement is that the entire instruction (or at least the first
-  XLEN bits) are fetched into {\tt mbadbits} before taking the trap.
+  XLEN bits) are fetched into {\tt mtval} before taking the trap.
   This should not constrain implementations, which would typically
   fetch the entire instruction before attempting to decode the
   instruction, and avoids complicating software handlers.
 
-  A value of zero in {\tt mbadbits} signifies either that the feature is
+  A value of zero in {\tt mtval} signifies either that the feature is
   not supported, or an illegal zero instruction was fetched.  A load
   from the instruction memory pointed to by {\tt mepc} can be used to
   distinguish these two cases (or alternatively, the system
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex
index 02298e4..c163409 100644
--- a/src/priv-csrs.tex
+++ b/src/priv-csrs.tex
@@ -159,7 +159,7 @@ Number    & Privilege & Name & Description \\
 \tt 0x040 & URW  &\tt uscratch   & Scratch register for user trap handlers. \\
 \tt 0x041 & URW  &\tt uepc       & User exception program counter. \\
 \tt 0x042 & URW  &\tt ucause     & User trap cause. \\
-\tt 0x043 & URW  &\tt ubadbits   & User bad address or instruction. \\
+\tt 0x043 & URW  &\tt utval      & User bad address or instruction. \\
 \tt 0x044 & URW  &\tt uip        & User interrupt pending. \\
 \hline
 \multicolumn{4}{|c|}{User Floating-Point CSRs} \\
@@ -212,7 +212,7 @@ Number    & Privilege & Name & Description \\
 \tt 0x140 & SRW  &\tt sscratch   & Scratch register for supervisor trap handlers. \\
 \tt 0x141 & SRW  &\tt sepc       & Supervisor exception program counter. \\
 \tt 0x142 & SRW  &\tt scause     & Supervisor trap cause. \\
-\tt 0x143 & SRW  &\tt sbadbits   & Supervisor bad address. \\
+\tt 0x143 & SRW  &\tt stval      & Supervisor bad address or instruction. \\
 \tt 0x144 & SRW  &\tt sip        & Supervisor interrupt pending. \\
 \hline
 \multicolumn{4}{|c|}{Supervisor Protection and Translation} \\
@@ -245,7 +245,7 @@ Number    & Privilege & Name & Description \\
 %% \tt 0x240 & HRW  &\tt hscratch   & Scratch register for hypervisor trap handlers. \\
 %% \tt 0x241 & HRW  &\tt hepc       & Hypervisor exception program counter. \\
 %% \tt 0x242 & HRW  &\tt hcause     & Hypervisor trap cause. \\
-%% \tt 0x243 & HRW  &\tt hbadbits   & Hypervisor bad address or instruction. \\
+%% \tt 0x243 & HRW  &\tt htval   & Hypervisor bad address or instruction. \\
 %% \tt 0x244 & HRW  &\tt hip        & Hypervisor interrupt pending. \\
 %% \hline
 %% \multicolumn{4}{|c|}{Hypervisor Protection and Translation} \\
@@ -287,7 +287,7 @@ Number    & Privilege & Name & Description \\
 \tt 0x340 & MRW  &\tt mscratch   & Scratch register for machine trap handlers. \\
 \tt 0x341 & MRW  &\tt mepc       & Machine exception program counter. \\
 \tt 0x342 & MRW  &\tt mcause     & Machine trap cause. \\
-\tt 0x343 & MRW  &\tt mbadbits   & Machine bad address or instruction. \\
+\tt 0x343 & MRW  &\tt mtval      & Machine bad address or instruction. \\
 \tt 0x344 & MRW  &\tt mip        & Machine interrupt pending. \\
 \hline
 \multicolumn{4}{|c|}{Machine Protection and Translation} \\
diff --git a/src/priv-preface.tex b/src/priv-preface.tex
index b660136..ec179fe 100644
--- a/src/priv-preface.tex
+++ b/src/priv-preface.tex
@@ -21,7 +21,7 @@ architecture proposal.  Changes from version 1.9.1 include:
   field previously called Base in {\tt misa} has been renamed to {\tt
     MXL} for consistency.
   \item The {\tt mbadaddr} register has been subsumed by a more
-    general {\tt mbadbits} register that can now capture bad
+    general {\tt mtval} register that can now capture bad
     instruction bits on an illegal instruction fault to speed
     instruction emulation.
 \item The machine-mode base-and-bounds translation and protection