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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2020-03-03 18:29:01 -0800 |
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| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2020-03-03 18:29:01 -0800 |
| commit | fc44561b65313ab81985f3cdf0b80d3a8b9c46f6 (patch) | |
| tree | 3fec52ebc6a0e7e0af54063e10ca70737644c807 | |
| parent | 2170a7188e556ae5343db8e1b6ca69b221077f16 (diff) | |
| download | riscv-isa-manual-fc44561b65313ab81985f3cdf0b80d3a8b9c46f6.zip riscv-isa-manual-fc44561b65313ab81985f3cdf0b80d3a8b9c46f6.tar.gz riscv-isa-manual-fc44561b65313ab81985f3cdf0b80d3a8b9c46f6.tar.bz2 | |
Refined definition of WARL.
Closes #333.
| -rw-r--r-- | src/priv-csrs.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index 4c6f065..fa6be96 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -447,7 +447,7 @@ values to a \warl\ field. Implementations can return any legal value on the read of a \warl\ field when the last write was of an illegal value, but the legal value returned should deterministically depend on the illegal written value and -the value of the field prior to the write. +the architectural state of the hart. \section{CSR Width Modulation} \label{sec:csrwidthmodulation} |