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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-29 14:48:10 -0700 |
|---|---|---|
| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-29 14:48:10 -0700 |
| commit | ebeb14b4259e078097a2fb07aa25bdecc2e9e4d6 (patch) | |
| tree | 9bdc177de9f196197e7a61a37cdc36e494399d52 | |
| parent | 3c8d95243aea56c97161412f3f0a2fa24139cadf (diff) | |
| download | riscv-isa-manual-ebeb14b4259e078097a2fb07aa25bdecc2e9e4d6.zip riscv-isa-manual-ebeb14b4259e078097a2fb07aa25bdecc2e9e4d6.tar.gz riscv-isa-manual-ebeb14b4259e078097a2fb07aa25bdecc2e9e4d6.tar.bz2 | |
Generalized description of counter behavior when not accessible.
| -rw-r--r-- | src/machine.tex | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/machine.tex b/src/machine.tex index 9189a81..8ca2059 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1626,9 +1626,7 @@ counters to the next-lowest privileged mode. The settings in these registers only control accessibility. The act of reading or writing these registers, does not affect the underlying -counters, except for the expected side effects of any instruction -execution (i.e., {\tt instret} will be incremented after a write to -these CSRs). +counters, which continue to increment even when not accessible. When the CY, TM, IR, or HPM{\em n} bit in the {\tt mcounteren} register is clear, attempts to read the {\tt cycle}, {\tt time}, {\tt |