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author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-09 19:12:39 -0700 |
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committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-09 19:12:39 -0700 |
commit | ebe5a516dfd9335c1b02bc7ac76d2a9f56f45704 (patch) | |
tree | 558f1f3efbdf77a2a6b1111e127ebef5a2a82a42 | |
parent | 53329a161c0d8ac9ded0920c259c0b82bf7501a1 (diff) | |
download | riscv-isa-manual-ebe5a516dfd9335c1b02bc7ac76d2a9f56f45704.zip riscv-isa-manual-ebe5a516dfd9335c1b02bc7ac76d2a9f56f45704.tar.gz riscv-isa-manual-ebe5a516dfd9335c1b02bc7ac76d2a9f56f45704.tar.bz2 |
Added description of hardware performance counters.
-rw-r--r-- | src/counters.tex | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/counters.tex b/src/counters.tex index adc8e0c..65c95b7 100644 --- a/src/counters.tex +++ b/src/counters.tex @@ -182,3 +182,24 @@ values atomically, but this would increase the size of the user context, especially for implementations with a richer set of counters. \end{commentary} +\section{Hardware Performance Counters} + +There is CSR space allocated for 29 additional unprivileged 64-bit +hardware performance counters, {\tt hpmcounter3}--{\tt hpmcounter31}. +For RV32, the upper 32 bits of these performance counters is +accessible via additional CSRs {\tt hpmcounter3h}--{\tt + hpmcounter31h}. These counters count platform-specific events and +are configured via additional privileged registers. The number and +width of these additional counters, and the set of events they count +is platform-specific. + +\begin{commentary} + The privileged architecture manual describes the privileged CSRs + controlling access to these counters and to set the events to be + counted. + + It would be useful to eventually standardize event settings to count + ISA-level metrics, such as the number of floating-point instructions + executed for example, and possibly a few common microarchitectural + metrics, such as ``L1 instruction cache misses''. +\end{commentary} |