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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-29 01:58:22 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-29 01:58:22 -0700 |
| commit | da6a19d33d6dc48d63059ce1f5b677dd919c3c14 (patch) | |
| tree | 4dbeb13c20fb502371367bcbc962643360437a95 | |
| parent | f06c1edcf51779f6943b1e2ddbca2617280ccaf3 (diff) | |
| download | riscv-isa-manual-da6a19d33d6dc48d63059ce1f5b677dd919c3c14.zip riscv-isa-manual-da6a19d33d6dc48d63059ce1f5b677dd919c3c14.tar.gz riscv-isa-manual-da6a19d33d6dc48d63059ce1f5b677dd919c3c14.tar.bz2 | |
Fix typo
| -rw-r--r-- | src/supervisor.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index fd376ad..983ef21 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1119,7 +1119,7 @@ We specified multiple virtual memory systems for RV64 to relieve the tension between providing a large address space and minimizing address-translation cost. For many systems, \wunits{512}{GiB} of virtual-address space is ample, and so Sv39 suffices. Sv48 increases the virtual address space to -\wunits{256}{TiB}, but increases the phyiscal memory +\wunits{256}{TiB}, but increases the physical memory capacity dedicated to page tables, the latency of page-table traversals, and the size of hardware structures that store virtual addresses. \end{commentary} |