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| author | Andrew Waterman <andrew@sifive.com> | 2021-01-12 15:38:17 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-01-12 15:38:17 -0800 |
| commit | cec25e6f061476a5fd464b1ddddf2f646c7b9c57 (patch) | |
| tree | 8fa027519527d0d2ef7ba5b5ac2472dcf23dfcb2 | |
| parent | dce784ac656327ef4758f265f47c6b4280933158 (diff) | |
| download | riscv-isa-manual-cec25e6f061476a5fd464b1ddddf2f646c7b9c57.zip riscv-isa-manual-cec25e6f061476a5fd464b1ddddf2f646c7b9c57.tar.gz riscv-isa-manual-cec25e6f061476a5fd464b1ddddf2f646c7b9c57.tar.bz2 | |
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| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index b409f7c..c3999d1 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1525,7 +1525,7 @@ the value of the SEIP bit returned in the {\tt rd} destination register is the logical-OR of the software-writable bit and the interrupt signal from the interrupt controller, but the signal from the interrupt controller is not used to calculate the value written to SEIP. -Only the software-writeable SEIP bit participates in the +Only the software-writable SEIP bit participates in the read-modify-write sequence of a CSRRS or CSRRC instruction. \begin{commentary} |