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authorAndrew Waterman <andrew@sifive.com>2020-10-17 14:51:47 -0700
committerAndrew Waterman <andrew@sifive.com>2020-10-17 14:51:47 -0700
commitca0672bfa9e2da2b373dae538f9cf71c153e272a (patch)
tree6edfdc44e196f6db2ec028b4fdb5cf50cdddfaa1
parent041ab35f53ae565b6a19e3aa94c0e9b9d4289f1a (diff)
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Update HINT table to indicate PAUSE HINT allocation
-rw-r--r--src/rv32.tex10
1 files changed, 7 insertions, 3 deletions
diff --git a/src/rv32.tex b/src/rv32.tex
index a143ef0..bc5d433 100644
--- a/src/rv32.tex
+++ b/src/rv32.tex
@@ -1418,7 +1418,7 @@ simulation/emulation.
\begin{tabular}{|l|l|c|l|}
\hline
Instruction & Constraints & Code Points & Purpose \\ \hline \hline
- LUI & {\em rd}={\tt x0} & $2^{20}$ & \multirow{15}{*}{\em Reserved for future standard use} \\ \cline{1-3}
+ LUI & {\em rd}={\tt x0} & $2^{20}$ & \multirow{19}{*}{\em Reserved for future standard use} \\ \cline{1-3}
AUIPC & {\em rd}={\tt x0} & $2^{20}$ & \\ \cline{1-3}
\multirow{2}{*}{ADDI} & {\em rd}={\tt x0}, and either & \multirow{2}{*}{$2^{17}-1$} & \\
& {\em rs1}$\neq${\tt x0} or {\em imm}$\neq$0 & & \\ \cline{1-3}
@@ -1433,8 +1433,12 @@ simulation/emulation.
SLL & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3}
SRL & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3}
SRA & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3}
- \multirow{2}{*}{FENCE}& {\em fm=0}, and either & \multirow{2}{*}{$2^{5}-1$} & \\
- & {\em pred}=0 or {\em succ}=0 & & \\ \hline \hline
+ \multirow{2}{*}{FENCE}& {\em fm=0}, & \multirow{2}{*}{15} & \\
+ & {\em pred}=0, {\em succ}$\neq$0 & & \\ \cline{1-3}
+ \multirow{2}{*}{FENCE}& {\em fm=0}, & \multirow{2}{*}{15} & \\
+ & {\em pred}$\neq$W, {\em succ}=0 & & \\ \hline
+ \multirow{2}{*}{FENCE}& {\em fm=0}, & \multirow{2}{*}{1} & \multirow{2}{*}{PAUSE} \\
+ & {\em pred}=W, {\em succ}=0 & & \\ \hline \hline
SLTI & {\em rd}={\tt x0} & $2^{17}$ & \multirow{7}{*}{\em Designated for custom use} \\ \cline{1-3}
SLTIU & {\em rd}={\tt x0} & $2^{17}$ & \\ \cline{1-3}
SLLI & {\em rd}={\tt x0} & $2^{10}$ & \\ \cline{1-3}