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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-06 23:00:07 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-06 23:00:07 -0800 |
| commit | c17a3fddbb8d0cb334669bf2925fc8fead22cf7e (patch) | |
| tree | a6e66e155c389180780ee68c6fafa4ff1a0176c5 | |
| parent | dd025a1ad39edcc2dc8f9efc59ebcb900706df07 (diff) | |
| download | riscv-isa-manual-c17a3fddbb8d0cb334669bf2925fc8fead22cf7e.zip riscv-isa-manual-c17a3fddbb8d0cb334669bf2925fc8fead22cf7e.tar.gz riscv-isa-manual-c17a3fddbb8d0cb334669bf2925fc8fead22cf7e.tar.bz2 | |
fix typo
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index 13bd358..a862fec 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -960,7 +960,7 @@ In systems with two privilege modes (M/U) and support for U-mode traps, setting a bit in {\tt medeleg} or {\tt mideleg} will delegate the corresponding trap in U-mode to the U-mode trap handler. -If systems with only M-mode, or with both M-mode and U-mode but +In systems with only M-mode, or with both M-mode and U-mode but without U-mode trap support, the {\tt medeleg} and {\tt mideleg} registers should be hardwired to zero. |