subset -> extension

5 files changed, 21 insertions, 21 deletions

diff --git a/src/a.tex b/src/a.tex
index 163c52f..c733790 100644
--- a/src/a.tex
+++ b/src/a.tex
@@ -1,8 +1,8 @@
 \chapter{``A'' Standard Extension for Atomic Instructions, Version 2.0}
 \label{atomics}
 
-The standard atomic instruction extension is denoted by instruction
-subset name ``A'', and contains instructions that atomically
+The standard atomic-instruction extension, named ``A'',
+contains instructions that atomically
 read-modify-write memory to support synchronization between multiple
 RISC-V harts running in the same memory space.  The two forms of
 atomic instruction provided are load-reserved/store-conditional
@@ -149,7 +149,7 @@ sequence plus the code to retry the sequence in case of failure must
 comprise at most 16 integer instructions placed sequentially in
 memory.  For the sequence to be guaranteed to eventually succeed, the
 dynamic code executed between the LR and SC instructions can only
-contain other instructions from the base ``I'' subset, excluding
+contain other instructions from the base ``I'' instruction set, excluding
 loads, stores, backward jumps or taken backward branches, FENCE,
 FENCE.I, and SYSTEM instructions.  The code to retry a failing LR/SC
 sequence can contain backward jumps and/or branches to repeat the
diff --git a/src/c.tex b/src/c.tex
index 6d49253..d0e1333 100644
--- a/src/c.tex
+++ b/src/c.tex
@@ -195,8 +195,8 @@ formats to allow access to all 32 data registers. CIW supplies an
 The RISC-V ABI was changed to make the frequently used registers map
 to registers {\tt x8}--{\tt x15}.  This simplifies the decompression
 decoder by having a contiguous naturally aligned set of register
-numbers, and is also compatible with the RV32E subset base
-specification, which only has 16 integer registers.
+numbers, and is also compatible with the RV32E base ISA,
+which only has 16 integer registers.
 \end{commentary}
 
 Compressed register-based floating-point loads and stores also use the
diff --git a/src/naming.tex b/src/naming.tex
index 43d62a4..f556fd7 100644
--- a/src/naming.tex
+++ b/src/naming.tex
@@ -1,7 +1,7 @@
-\chapter{ISA Subset Naming Conventions}
+\chapter{ISA Extension Naming Conventions}
 \label{naming}
 
-This chapter describes the RISC-V ISA subset naming scheme that is
+This chapter describes the RISC-V ISA extension naming scheme that is
 used to concisely describe the set of instructions present in a
 hardware implementation, or the set of instructions used by an
 application binary interface (ABI).
@@ -45,7 +45,7 @@ letters, e.g., ``Q'' for quad-precision floating-point, or
 
 \section{Version Numbers}
 Recognizing that instruction sets may expand or alter over time, we
-encode subset version numbers following the subset name.  Version
+encode extension version numbers following the extension name.  Version
 numbers are divided into major and minor version numbers, separated by
 a ``p''.  If the minor version is ``0'', then ``p0'' can be omitted
 from the version string.  Changes in major version numbers imply a
@@ -54,18 +54,18 @@ version number must be backwards-compatible.  For example, the
 original 64-bit standard ISA defined in release 1.0 of this manual can
 be written in full as ``RV64I1p0M1p0A1p0F1p0D1p0'', more concisely as
 ``RV64I1M1A1F1D1'', or even more concisely as ``RV64G1''.  The G ISA
-subset can be written as ``RV64I2p0M2p0A2p0F2p0D2p0'', or more
+can be written as ``RV64I2p0M2p0A2p0F2p0D2p0'', or more
 concisely ``RV64G2''.
 
 We introduced the version numbering scheme with the second release,
 which we also intend to become a permanent standard.  Hence, we define
-the default version of a standard subset to be that present at the
+the default version of a standard extension to be that present at the
 time of this document, e.g., ``RV32G'' is equivalent to
 ``RV32I2M2A2F2D2''.
 
 \section{Underscores}
 
-Underscores ``\_'' may be used to separate ISA subset components to
+Underscores ``\_'' may be used to separate ISA extensions to
 improve readability and to provide disambiguation. For example, ``RV32I2\_M2\_A2\_F2\_D2''.
 
 \section{Additional Standard Extension Names}
@@ -82,7 +82,7 @@ from other multi-letter extensions by an underscore, e.g.,
 
 \section{Non-Standard Extension Names}
 
-Non-standard subsets are named using a single ``X'' followed by an
+Non-standard extensions are named using a single ``X'' followed by an
 alphabetical name and an optional version number.
 For example, ``Xhwacha'' names the Hwacha vector-fetch ISA extension;
 ``Xhwacha2'' and ``Xhwacha2p0'' name version 2.0 of same.
@@ -104,7 +104,7 @@ Non-standard extensions to the supervisor-level ISA are defined using
 the ``SX'' prefix.
 
 \section{Subset Naming Convention}
-Table~\ref{isanametable} summarizes the standardized subset names.
+Table~\ref{isanametable} summarizes the standardized extension names.
 ~\\
 \begin{table}[h]
 \center
@@ -151,8 +151,8 @@ Supervisor extension ``def'' & Sdef \\
 Supervisor extension ``ghi'' & SXghi \\
 \hline
 \end{tabular}
-\caption{Standard ISA subset names.  The table also defines the
-  canonical order in which subset names must appear in the name
+\caption{Standard ISA extension names.  The table also defines the
+  canonical order in which extension names must appear in the name
   string, with top-to-bottom in table indicating first-to-last in the
   name string, e.g., RV32IMAFDQC is legal, whereas RV32IMAFDCQ is not.}
 \label{isanametable}
diff --git a/src/p.tex b/src/p.tex
index b360294..074e475 100644
--- a/src/p.tex
+++ b/src/p.tex
@@ -12,7 +12,7 @@
 \end{commentary}
 
 In this chapter, we outline a standard packed-SIMD extension for
-RISC-V.  We've reserved the instruction subset name ``P'' for a future
+RISC-V.  We've reserved the instruction-set extension name ``P'' for a future
 standard set of packed-SIMD extensions.  Many other extensions can
 build upon a packed-SIMD extension, taking advantage of the wide data
 registers and datapaths separate from the integer unit.
@@ -39,8 +39,8 @@ architectures are a better choice and should use the V extension.
 
 A RISC-V packed-SIMD extension reuses the floating-point registers
 ({\tt f0}-{\tt f31}).  These registers can be defined to have widths
-of FLEN=32 to FLEN=1024.  The standard floating-point instruction
-subsets require registers of width 32 bits (``F''), 64 bits (``D''),
+of FLEN=32 to FLEN=1024.  The standard floating-point instruction-set
+extensions require registers of width 32 bits (``F''), 64 bits (``D''),
 or 128 bits (``Q'').
 
 \begin{commentary}
diff --git a/src/q.tex b/src/q.tex
index b248cc3..bdc3d51 100644
--- a/src/q.tex
+++ b/src/q.tex
@@ -1,10 +1,10 @@
 \chapter{``Q'' Standard Extension for Quad-Precision Floating-Point,
   Version 2.2}
 
-This chapter describes the Q standard extension for 128-bit binary
+This chapter describes the Q standard extension for 128-bit quad-precision binary
 floating-point instructions compliant with the IEEE 754-2008
-arithmetic standard. The 128-bit or quad-precision binary
-floating-point instruction subset is named ``Q'', and requires
+arithmetic standard. The quad-precision binary
+floating-point instruction-set extension is named ``Q'', and requires
 RV64IFD.  The floating-point registers are now extended to hold either
 a single, double, or quad-precision floating-point value (FLEN=128).
 The NaN-boxing scheme described in Section~\ref{nanboxing} is now