Define semantics for contradictory misa settings (#285)

* Define semantics for contradictory misa settings

Closes #82

* Add commentary about contradictor misa settings

1 files changed, 16 insertions, 0 deletions

diff --git a/src/machine.tex b/src/machine.tex
index 539838f..2e88a1f 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -176,6 +176,22 @@ ISA observed at any level, and supports a much richer command
 interface without burdening hardware designs.
 \end{commentary}
 
+Unless {\tt misa} is hardwired to zero, the I and E bits are always
+complements of each other.  Hence, either both are read-only or both are
+writable.  If they are writable, then an attempt to set them to the same value
+{\em x} causes I to be set to {\em x} and E to be set to !{\em x}.
+
+The implementation may impose additional constraints on the collective setting
+of two or more {\tt misa} fields, in which case they function collectively as
+a single \warl\ field.  For example, an implementation might require that the
+D bit be clear unless the F bit is set.  An attempt to write an unsupported
+combination causes those bits to be set to some supported combination.
+\begin{commentary}
+In the event that an unsupported combination is written to {\tt misa},
+it is recommended that the implementation select the supported combination
+with the fewest features enabled, to aid debugging of the error.
+\end{commentary}
+
 Writing {\tt misa} may increase IALIGN, e.g., by disabling the ``C''
 extension.
 If an instruction that would write {\tt misa} increases IALIGN, and