Priority of misaligned load/store address checks is implementation-defined

2 files changed, 21 insertions, 1 deletions

diff --git a/src/machine.tex b/src/machine.tex
index 0ea6820..7853356 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -2165,12 +2165,14 @@ The priority of any custom synchronous exceptions is implementation-defined.
                 &   8, 9, 11 & Environment call \\
                 &          3 & Environment break \\
                 &          3 & Load/Store/AMO address breakpoint \\ \hline
+  {\em Optionally, these may have}
                 &          6 & Store/AMO address misaligned \\
+  {\em lowest priority instead.}
                 &          4 & Load address misaligned \\ \hline
                 &         15 & Store/AMO page fault \\
                 &         13 & Load page fault \\ \hline
                 &          7 & Store/AMO access fault \\
-  {\em Lowest}  &          5 & Load access fault \\
+                &          5 & Load access fault \\
   \hline
 
 \end{tabular}
@@ -2179,6 +2181,21 @@ The priority of any custom synchronous exceptions is implementation-defined.
 \label{exception-priority}
 \end{table*}
 
+Note that load/store/AMO address-misaligned and page-fault exceptions may have
+either higher or lower priority than load/store/AMO page faults and access
+faults.
+\begin{commentary}
+The relative priority of load/store/AMO address-misaligned and page-fault
+exceptions is implementation-defined to flexibly cater to two design points.
+Implementations that never support misaligned accesses can unconditionally
+raise the misaligned-address exception without performing address translation
+or protection checks.
+Implementations that support misaligned accesses only to some physical
+addresses must translate and check the address before determining whether the
+misaligned access may proceed, in which case raising the page-fault exception
+or access is more appropriate.
+\end{commentary}
+
 \begin{commentary}
 Instruction address breakpoints have the same cause value as, but
 different priority than, data address breakpoints (a.k.a. watchpoints)
diff --git a/src/priv-preface.tex b/src/priv-preface.tex
index 19a2d63..e18d9d3 100644
--- a/src/priv-preface.tex
+++ b/src/priv-preface.tex
@@ -55,6 +55,9 @@ Additionally, the following compatible changes have been made since version
   same fields as the upper 32 bits of RV64's {\tt mstatus}.
 \item Permitted the unconditional delegation of less-privileged interrupts.
 \item Added optional big-endian and bi-endian support.
+\item Made priority of load/store/AMO address-misaligned exceptions
+  implementation-defined relative to load/store/AMO page-fault
+  and access-fault exceptions.
 \end{itemize}
 
 Finally, the hypervisor architecture proposal has been extensively revised.