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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-13 16:04:38 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-13 16:04:38 -0700 |
| commit | 8bb62be82d1301e7fc17edde0f4efec12dfb5001 (patch) | |
| tree | 4388ffe8b64df45a5d5904332fe1998d83b10100 | |
| parent | 7b7361ae364cb3a7268c3a5abb61b1caac8fa7fe (diff) | |
| download | riscv-isa-manual-8bb62be82d1301e7fc17edde0f4efec12dfb5001.zip riscv-isa-manual-8bb62be82d1301e7fc17edde0f4efec12dfb5001.tar.gz riscv-isa-manual-8bb62be82d1301e7fc17edde0f4efec12dfb5001.tar.bz2 | |
Add TSR mechanism
| -rw-r--r-- | src/machine.tex | 27 |
1 files changed, 21 insertions, 6 deletions
diff --git a/src/machine.tex b/src/machine.tex index 4809f83..6e25f98 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -322,10 +322,11 @@ privilege-level ISAs respectively. {\footnotesize \begin{center} \setlength{\tabcolsep}{4pt} -\begin{tabular}{cKcccccc} +\begin{tabular}{cKccccccc} \\ \instbit{31} & -\instbitrange{30}{22} & +\instbitrange{30}{23} & +\instbit{22} & \instbit{21} & \instbit{20} & \instbit{19} & @@ -335,6 +336,7 @@ privilege-level ISAs respectively. \hline \multicolumn{1}{|c|}{SD} & \multicolumn{1}{c|}{\wpri} & +\multicolumn{1}{c|}{TSR} & \multicolumn{1}{c|}{TW} & \multicolumn{1}{c|}{TVM} & \multicolumn{1}{c|}{MXR} & @@ -342,7 +344,7 @@ privilege-level ISAs respectively. \multicolumn{1}{c|}{MPRV} & \\ \hline -1 & 9 & 1 & 1 & 1 & 1 & 1 & \\ +1 & 9 & 1 & 1 & 1 & 1 & 1 & 1 & \\ \end{tabular} \begin{tabular}{cccccccccccccc} \\ @@ -389,13 +391,14 @@ privilege-level ISAs respectively. {\footnotesize \begin{center} \setlength{\tabcolsep}{4pt} -\begin{tabular}{cSccScccccc} +\begin{tabular}{cSccSccccccc} \\ \instbit{XLEN-1} & \instbitrange{XLEN-2}{36} & \instbitrange{35}{34} & \instbitrange{33}{32} & -\instbitrange{31}{22} & +\instbitrange{31}{23} & +\instbit{22} & \instbit{21} & \instbit{20} & \instbit{19} & @@ -408,6 +411,7 @@ privilege-level ISAs respectively. \multicolumn{1}{c|}{SXL} & \multicolumn{1}{c|}{UXL} & \multicolumn{1}{c|}{\wpri} & +\multicolumn{1}{c|}{TSR} & \multicolumn{1}{c|}{TW} & \multicolumn{1}{c|}{TVM} & \multicolumn{1}{c|}{MXR} & @@ -415,7 +419,7 @@ privilege-level ISAs respectively. \multicolumn{1}{c|}{MPRV} & \\ \hline -1 & XLEN-37 & 2 & 2 & 10 & 1 & 1 & 1 & 1 & 1 & \\ +1 & XLEN-37 & 2 & 2 & 10 & 1 & 1 & 1 & 1 & 1 & 1 & \\ \end{tabular} \begin{tabular}{cccccccccccccc} \\ @@ -628,6 +632,17 @@ instruction can trigger a world switch to another guest OS, rather than wastefully idling in the current guest. \end{commentary} +The TSR (Trap SRET) bit supports intercepting the supervisor exception return +instruction, SRET. When TSR=1, attempts execute SRET while executing in +S-mode will raise an illegal instruction exception. When TSR=0, this +operation is permitted in S-mode. TSR is hard-wired to 0 when S-mode is not +supported. + +\begin{commentary} +Trapping SRET is necessary to emulate the Augmented Virtualization mechanism +(see Chapter~\ref{hypervisor}) on implementations that do not provide it. +\end{commentary} + \subsection{Extension Context Status in {\tt mstatus} Register} Supporting substantial extensions is one of the primary goals of |