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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2017-03-20 04:22:08 -0700 |
|---|---|---|
| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2017-03-20 04:22:08 -0700 |
| commit | 7c0626f5e6d47488676a2f06d3dbf17a89d4cbae (patch) | |
| tree | 2d68541203b3f6dfed62c5e26033a281c055ab66 | |
| parent | 76f3c072674a3a3b0eeefe767ca1b52107998c8d (diff) | |
| download | riscv-isa-manual-7c0626f5e6d47488676a2f06d3dbf17a89d4cbae.zip riscv-isa-manual-7c0626f5e6d47488676a2f06d3dbf17a89d4cbae.tar.gz riscv-isa-manual-7c0626f5e6d47488676a2f06d3dbf17a89d4cbae.tar.bz2 | |
Now mideleg /medeleg only exist if lower privilege mode exists and can take traps, whereas before they were present and zero.
| -rw-r--r-- | src/machine.tex | 11 | ||||
| -rw-r--r-- | src/priv-preface.tex | 3 |
2 files changed, 12 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index ae66c95..240dd75 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -978,7 +978,14 @@ delegate the corresponding trap in U-mode to the U-mode trap handler. In systems with only M-mode, or with both M-mode and U-mode but without U-mode trap support, the {\tt medeleg} and {\tt mideleg} -registers should be hardwired to zero. +registers should not exist. +\begin{commentary} + In versions 1.9.1 and earlier , these registers existed but were + hardwired to zero in M-mode only, or M/U without N systems. There + is no reason to require they return zero in those cases, as the {\tt + misa} register indicates whether they exist. +\end{commentary} + When a trap is delegated to a less-privileged mode {\em x}, the {\em x}\,{\tt cause} register is written with the trap cause; the @@ -1051,7 +1058,7 @@ layout of bits matching those in the {\tt mip} register (i.e., STIP interrupt delegation control is located in bit 5). Some exceptions cannot occur at less privileged modes, and corresponding -{\em x}{\tt edeleg} bits should be hardwired to zero. In particular, +{\em x}\,{\tt edeleg} bits should be hardwired to zero. In particular, {\tt medeleg}[11] and {\tt sedeleg}[11:9] are all hardwired to zero. \subsection{Machine Interrupt Registers ({\tt mip} and {\tt mie})} diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 0cee249..8f24da9 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -16,6 +16,9 @@ architecture proposal. Changes from version 1.9.1 include: \item An optional mechanism to change the base ISA used by supervisor and user modes has been added, and the field previously called Base in {\tt misa} has been renamed to {\tt MXL} for consistency. +\item In systems with only M-mode, or with both M-mode and U-mode but + without U-mode trap support, the {\tt medeleg} and {\tt mideleg} + registers now do not exist, whereas previously they returned zero. \item The supervisor virtual memory configuration has been moved from the {\tt mstatus} register to the {\tt sptbr} register. \item The SFENCE.VM instruction has been removed in favor of the improved |