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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-19 20:30:43 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-19 20:30:43 -0700 |
| commit | 78803026566f11dc2d9aec390b597101ec0b5731 (patch) | |
| tree | e10ce9f1bc2b3a922b89f2c47fd3392fbe3af03f | |
| parent | 14f269d349d4e0f211752b3217bf7958ed6fc5d2 (diff) | |
| download | riscv-isa-manual-78803026566f11dc2d9aec390b597101ec0b5731.zip riscv-isa-manual-78803026566f11dc2d9aec390b597101ec0b5731.tar.gz riscv-isa-manual-78803026566f11dc2d9aec390b597101ec0b5731.tar.bz2 | |
fix typo
| -rw-r--r-- | src/priv-preface.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 04b6254..346e2a4 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -11,7 +11,7 @@ architecture proposal. Changes from version 1.9.1 include: original authors, and this and future versions of this document will be released under the same licence. \item The interrupt-enable stack discipline has been simplified. -\item A optional mechanism to change the base ISA used by supervisor +\item An optional mechanism to change the base ISA used by supervisor and user modes has been added, and the field previously called Base in {\tt misa} has been renamed to {\tt MXL} for consistency. \item The supervisor virtual memory configuration has been moved from the @@ -22,7 +22,7 @@ architecture proposal. Changes from version 1.9.1 include: been made optional; simpler implementations may trap to software to set them. \item The counter-enable scheme has changed, so that S-mode can - control availability of counters to U-mode, respectively. + control availability of counters to U-mode. \item H-mode has been removed, as we are focusing on recursive virtualization support in S-mode. The encoding space has been reserved and may be repurposed at a later date. |