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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-20 01:15:15 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-20 01:20:01 -0700 |
| commit | 727914cc3d553851dbf572a2aff52aa4ef0b7841 (patch) | |
| tree | f66e5cc440e7a19c1a1f3ff5720b2fed21a2c1cb | |
| parent | 682530ca4aebc770e8da9959c4d7a622c1ed5c81 (diff) | |
| download | riscv-isa-manual-727914cc3d553851dbf572a2aff52aa4ef0b7841.zip riscv-isa-manual-727914cc3d553851dbf572a2aff52aa4ef0b7841.tar.gz riscv-isa-manual-727914cc3d553851dbf572a2aff52aa4ef0b7841.tar.bz2 | |
Add changelog entries for PUM -> SUM and MXR
| -rw-r--r-- | src/priv-preface.tex | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 346e2a4..437b21e 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -28,6 +28,9 @@ architecture proposal. Changes from version 1.9.1 include: reserved and may be repurposed at a later date. \item A mechanism to improve virtualization performance by trapping S-mode virtual-memory management operations has been added. +\item The {\tt mstatus} bit MXR has been exposed to S-mode via {\tt sstatus}. +\item The polarity of the PUM bit in {\tt sstatus} has been inverted to + shorten code sequences involving MXR. The bit has been renamed to SUM. \end{itemize} \newpage |