aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAndrew Waterman <andrew@sifive.com>2018-11-26 15:13:05 -0800
committerAndrew Waterman <andrew@sifive.com>2018-11-26 15:13:05 -0800
commit6e34c135660bee09210c1af2c9502042f0998f44 (patch)
treed4cc3373ad0be25bf3cd1103846c04b46a6ac2dc
parent48994717131369d5ecbe1960263325c428917deb (diff)
downloadriscv-isa-manual-6e34c135660bee09210c1af2c9502042f0998f44.zip
riscv-isa-manual-6e34c135660bee09210c1af2c9502042f0998f44.tar.gz
riscv-isa-manual-6e34c135660bee09210c1af2c9502042f0998f44.tar.bz2
Clarify that bits 16 and up of *ip/*ie are "custom"
Closes #271.
-rw-r--r--src/machine.tex32
1 files changed, 18 insertions, 14 deletions
diff --git a/src/machine.tex b/src/machine.tex
index bb0928c..1768a5c 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1202,11 +1202,12 @@ bits in {\em x}\,{\tt ip} and {\em x}\,{\tt ie} appear to be hardwired
to zero.
\begin{figure*}[h!]
-{\footnotesize
+{\scriptsize
\begin{center}
\setlength{\tabcolsep}{4pt}
-\begin{tabular}{Rcccccccccccc}
-\instbitrange{MXLEN-1}{12} &
+\begin{tabular}{Rccccccccccccc}
+\instbitrange{MXLEN-1}{16} &
+\instbitrange{15}{12} &
\instbit{11} &
\instbit{10} &
\instbit{9} &
@@ -1220,7 +1221,8 @@ to zero.
\instbit{1} &
\instbit{0} \\
\hline
-\multicolumn{1}{|c|}{\wpri} &
+\multicolumn{1}{|c|}{\em Res. Custom} &
+\multicolumn{1}{c|}{\wpri} &
\multicolumn{1}{c|}{MEIP} &
\multicolumn{1}{c|}{\wpri} &
\multicolumn{1}{c|}{SEIP} &
@@ -1234,7 +1236,7 @@ to zero.
\multicolumn{1}{c|}{SSIP} &
\multicolumn{1}{c|}{USIP} \\
\hline
-MXLEN-12 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
+MXLEN-16 & 4 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
\end{tabular}
\end{center}
}
@@ -1244,11 +1246,12 @@ MXLEN-12 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
\end{figure*}
\begin{figure*}[h!]
-{\footnotesize
+{\scriptsize
\begin{center}
\setlength{\tabcolsep}{4pt}
-\begin{tabular}{Rcccccccccccc}
-\instbitrange{MXLEN-1}{12} &
+\begin{tabular}{Rccccccccccccc}
+\instbitrange{MXLEN-1}{16} &
+\instbitrange{15}{12} &
\instbit{11} &
\instbit{10} &
\instbit{9} &
@@ -1262,7 +1265,8 @@ MXLEN-12 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
\instbit{1} &
\instbit{0} \\
\hline
-\multicolumn{1}{|c|}{\wpri} &
+\multicolumn{1}{|c|}{\em Res. Custom} &
+\multicolumn{1}{c|}{\wpri} &
\multicolumn{1}{c|}{MEIE} &
\multicolumn{1}{c|}{\wpri} &
\multicolumn{1}{c|}{SEIE} &
@@ -1276,7 +1280,7 @@ MXLEN-12 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
\multicolumn{1}{c|}{SSIE} &
\multicolumn{1}{c|}{USIE} \\
\hline
-MXLEN-12 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
+MXLEN-16 & 4 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\
\end{tabular}
\end{center}
}
@@ -1371,10 +1375,10 @@ interrupt-enable bits are hardwired to zero in the {\tt mip} and {\tt
mie} registers respectively. Hence, these are all effectively
\warl\ fields.
-Implementations may add additional platform-specific machine-level
-interrupt sources to bits 16 and above of the {\tt mip} and {\tt mie}
-registers. The other unallocated interrupt sources (15--12, 10, 6, and 2)
-are reserved for future standard use.
+Implementations may add additional custom machine-level interrupt sources to
+bits 16 and above of the {\tt mip} and {\tt mie} registers. The other
+unallocated interrupt sources (15--12, 10, 6, and 2) are reserved for future
+standard use. The corresponding fields are all \wpri.
An interrupt {\em i} will be taken if bit {\em i} is set in both {\tt
mip} and {\tt mie}, and if interrupts are globally enabled. By