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| author | Andrew Waterman <andrew@sifive.com> | 2017-05-05 00:10:24 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-05-05 00:10:24 -0700 |
| commit | 6dd01786811910ae170ed4ffedb68b2edb7b8882 (patch) | |
| tree | 2b6a973a1f8a3adb0743ec3aceebca53dc00b8fb | |
| parent | b3d3009fa7f45fbf8b41713f510208caf88a246e (diff) | |
| download | riscv-isa-manual-6dd01786811910ae170ed4ffedb68b2edb7b8882.zip riscv-isa-manual-6dd01786811910ae170ed4ffedb68b2edb7b8882.tar.gz riscv-isa-manual-6dd01786811910ae170ed4ffedb68b2edb7b8882.tar.bz2 | |
Remove redundant clause in SFENCE.VMA description
| -rw-r--r-- | src/supervisor.tex | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 099915d..c043437 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -824,9 +824,7 @@ these data structures; however, these implicit references are ordinarily not ordered with respect to loads and stores in the instruction stream. Executing an SFENCE.VMA instruction guarantees that any stores in the instruction stream prior to the SFENCE.VMA are ordered before all implicit references subsequent -to the SFENCE.VMA. Furthermore, executing an SFENCE.VMA guarantees that any -implicit writes caused by instructions prior to the SFENCE.VMA are ordered -before all loads and stores subsequent to the SFENCE.VMA. +to the SFENCE.VMA. \begin{commentary} The SFENCE.VMA is used to flush any local hardware caches related to |