Merge pull request #139 from riscv/misa-c

Introduce IALIGN; propose misa.C semantics

4 files changed, 24 insertions, 17 deletions

diff --git a/src/c.tex b/src/c.tex
index 066c5ef..d13e27c 100644
--- a/src/c.tex
+++ b/src/c.tex
@@ -28,9 +28,9 @@ versions of common 32-bit RISC-V instructions when:
 The C extension is compatible with all other standard instruction
 extensions.  The C extension allows 16-bit instructions to be freely
 intermixed with 32-bit instructions, with the latter now able to start
-on any 16-bit boundary.  With the addition of the C extension, JAL and
-JALR instructions will no longer raise an instruction misaligned
-exception.
+on any 16-bit boundary, i.e., IALIGN=16.  With the addition of the C
+extension, no instructions can raise instruction-address-misaligned
+exceptions.
 
 \pagebreak
 
diff --git a/src/intro.tex b/src/intro.tex
index 142e358..d9e1f57 100644
--- a/src/intro.tex
+++ b/src/intro.tex
@@ -268,6 +268,12 @@ providing compressed 16-bit instructions and relaxes the alignment
 constraints to allow all instructions (16 bit and 32 bit) to be
 aligned on any 16-bit boundary to improve code density.
 
+We use the term IALIGN (measured in bits) to refer to the instruction-address
+alignment constraint the implementation enforces.  IALIGN is 32 bits in the
+base ISA, but some ISA extensions, including the compressed ISA extension,
+relax IALIGN to 16 bits.  IALIGN may not take on any value other than 16 or
+32.
+
 We use the term ILEN (measured in bits) to refer to the maximum
 instruction length supported by an implementation, and which is always
 a multiple of 16 bits.  For implementations supporting only a base
diff --git a/src/machine.tex b/src/machine.tex
index 222a92a..6479ce6 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -171,9 +171,11 @@ ISA observed at any level, and supports a much richer command
 interface without burdening hardware designs.
 \end{commentary}
 
-When clearing the ``C'' bit in {\tt misa}, software must ensure that the
-current {\tt pc} is 4-byte aligned and that all {\em x}{\tt epc} registers
-contain 4-byte-aligned values.
+Writing {\tt misa} may increase IALIGN, e.g., by disabling the ``C''
+extension.  If an instruction that writes {\tt misa} increases IALIGN, and the
+subsequent instruction's address is not IALIGN-bit aligned, the attempt to
+fetch that subsequent instruction raises an instruction-address-misaligned
+exception.
 
 \clearpage
 
@@ -1669,14 +1671,8 @@ Unlike the MIPS design, the OS can rely on holding a value in the {\tt
 
 {\tt mepc} is an XLEN-bit read/write register formatted as shown in
 Figure~\ref{mepcreg}.  The low bit of {\tt mepc} ({\tt mepc[0]}) is
-always zero.  On implementations that do not support instruction-set
-extensions with 16-bit instruction alignment, the two low bits ({\tt
-  mepc[1:0]}) are always zero.
-
-\begin{commentary}
-The {\tt mepc} register can never hold a PC value that would cause an
-instruction-address-misaligned exception.
-\end{commentary}
+always zero.  Implementations with IALIGN=32 may additionally
+hardwire {\tt mepc[1]} to zero.
 
 {\tt mepc} is a \warl\ register that must be able to hold all valid physical
 and virtual addresses.  It need not be capable of holding all possible invalid
@@ -2005,6 +2001,12 @@ It then became more orthogonal to support a different {\em x}RET
 instruction per privilege level.
 \end{commentary}
 
+The address held in the {\em x}\,{\tt epc} register has no effect on the
+success of an {\em x}\,RET instruction.  If the address held in {\em x}\,{\tt
+epc} is misaligned or otherwise invalid, an exception is raised on the
+instruction fetch subsequent to the retirement of the {\em x}\,RET
+instruction.
+
 \subsection{Wait for Interrupt}
 \label{wfi}
 
diff --git a/src/supervisor.tex b/src/supervisor.tex
index be8e5d6..e443612 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -538,9 +538,8 @@ XLEN \\
 
 {\tt sepc} is an XLEN-bit read/write register formatted as shown in
 Figure~\ref{epcreg}.  The low bit of {\tt sepc} ({\tt sepc[0]}) is
-always zero.  On implementations that do not support instruction-set
-extensions with 16-bit instruction alignment, the two low bits ({\tt
-  sepc[1:0]}) are always zero.
+always zero.  Implementations with IALIGN=32 may additionally
+hardwire {\tt sepc[1]} to zero.
 
 {\tt sepc} is a \warl\ register that must be able to hold all valid physical
 and virtual addresses.  It need not be capable of holding all possible invalid