Fix some orphaned/widowed commentary sections

6 files changed, 14 insertions, 10 deletions

diff --git a/src/d.tex b/src/d.tex
index a8decfe..2aee82b 100644
--- a/src/d.tex
+++ b/src/d.tex
@@ -32,7 +32,7 @@ NaN-boxing.  The upper bits of a valid NaN-boxed value must be all 1s.
 Valid NaN-boxed $n$-bit values therefore appear as negative quiet NaNs
 (qNaNs) when viewed as any wider $m$-bit value, \mbox{$n < m \leq$ FLEN}.
 
-\begin{commentary}
+\begin{samepage-commentary}
 Software might not know the current type of data stored in a
 floating-point register but has to be able to save and restore the
 register values, hence the result of using wider operations to
@@ -40,7 +40,7 @@ transfer narrower values has to be defined.  A common case is for
 callee-saved registers, but a standard convention is also desirable for
 features including varargs, user-level threading libraries, virtual
 machine migration, and debugging.
-\end{commentary}
+\end{samepage-commentary}
 
 Floating-point $n$-bit transfer operations move external values held
 in IEEE standard formats into and out of the {\tt f} registers, and
diff --git a/src/intro.tex b/src/intro.tex
index c531a2c..dc8f1b6 100644
--- a/src/intro.tex
+++ b/src/intro.tex
@@ -398,7 +398,7 @@ Byte Address: & \multicolumn{1}{r}{base+4} & \multicolumn{1}{r}{base+2} & \multi
 \label{instlengthcode}
 \end{figure}
 
-\begin{commentary}
+\begin{samepage-commentary}
 Given the code size and energy savings of a compressed format, we
 wanted to build in support for a compressed format to the ISA encoding
 scheme rather than adding this as an afterthought, but to allow
@@ -426,7 +426,7 @@ format, while preserving support for standard $>=$32-bit
 instruction-set extensions.  Further, if the implementation also does
 not need instructions $>$32-bits in length, it can recover a further
 four major opcodes.
-\end{commentary}
+\end{samepage-commentary}
 \begin{commentary}
 We consider it a feature that any length of instruction containing all
 zero bits is not legal, as this quickly traps erroneous jumps into
diff --git a/src/machine.tex b/src/machine.tex
index af59323..3a8ff5a 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1479,7 +1479,7 @@ mcycleh}, {\tt minstreth}, and {\tt mhpmcounter{\em n}h} CSRs return bits
 
 On RV128 systems, the 64-bit values in {\tt mcycle}, {\tt minstret}, and
 {\tt mhpmcounter{\em n}} are sign-extended to 128-bits when read.
-\begin{commentary}
+\begin{samepage-commentary}
 On RV128 systems, both signed and unsigned 64-bit values are held in a
 canonical form with bit 63 repeated in all higher bit positions.  The
 counters are 64-bit values even in RV128, and so the counter CSR reads
@@ -1488,7 +1488,7 @@ implement fewer bits of the counters, provided software would be unlikely
 to experience wraparound (e.g., $2^{63}$ instructions executed)
 and thereby avoid having to actually implement the sign-extension
 circuitry.
-\end{commentary}
+\end{samepage-commentary}
 
 \subsection{Counter-Enable Registers ({\tt [m|h|s]counteren})}
 \label{sec:mcounteren}
diff --git a/src/preamble.tex b/src/preamble.tex
index a64a354..7dbb45d 100644
--- a/src/preamble.tex
+++ b/src/preamble.tex
@@ -71,6 +71,10 @@
   \vspace{-0.2in}
 }
 
+\newenvironment{samepage-commentary}
+{\begin{samepage} \begin{commentary}}
+{\end{commentary} \end{samepage}}
+
 % Other commands and parameters
 
 \pagestyle{myheadings}
diff --git a/src/supervisor.tex b/src/supervisor.tex
index b3f0307..26073cc 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -746,13 +746,13 @@ values Sv39 and Sv48.}
 \label{rv64satp}
 \end{figure}
 
-\begin{commentary}
+\begin{samepage-commentary}
 We store the ASID and the page table base address in the same CSR to allow the
 pair to be changed atomically on a context switch.  Swapping them
 non-atomically could pollute the old virtual address space with new
 translations, or vice-versa.  This approach also slightly reduces the cost of
 a context switch.
-\end{commentary}
+\end{samepage-commentary}
 
 Table~\ref{tab:satp-mode} shows the encodings of the MODE field for RV32 and
 RV64.  When MODE=Bare, supervisor virtual addresses are equal to
diff --git a/src/v.tex b/src/v.tex
index 1b9dd9b..4d4e2d1 100644
--- a/src/v.tex
+++ b/src/v.tex
@@ -120,14 +120,14 @@ Section~\ref{sec:scalarhalffloat}.  The scalar half-precision
 instructions follow the template for other floating-point precisions,
 but using the hitherto unused {\em fmt} field encoding of {\tt 10}.
 
-\begin{commentary}
+\begin{samepage-commentary}
   We only support scalar half-precision floating-point types as part
   of the vector extension, as the main benefits of half-precision are
   obtained when using vector instructions that amortize per-operation
   control overhead.  Not supporting a separate scalar half-precision
   floating-point extension also reduces the number of standard
   instruction-set variants.
-\end{commentary}
+\end{samepage-commentary}
 
 \section{Vector Configuration Registers ({\tt vcmaxw}, {\tt
     vctype}, {\tt vcp})}