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author | Andrew Waterman <andrew@sifive.com> | 2019-11-05 22:21:38 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2019-11-05 22:21:38 -0800 |
commit | 47745d937e4ad9dbf02571fd083a716f528ca5df (patch) | |
tree | d72046b30266052ba935e050dd1bcdd77b5fe2f9 | |
parent | 899457caf7a9cdcb59a7d57421d249512b00de94 (diff) | |
download | riscv-isa-manual-47745d937e4ad9dbf02571fd083a716f528ca5df.zip riscv-isa-manual-47745d937e4ad9dbf02571fd083a716f528ca5df.tar.gz riscv-isa-manual-47745d937e4ad9dbf02571fd083a716f528ca5df.tar.bz2 |
Improve commentary environment page-break behavior
h/t JohnH
-rw-r--r-- | src/m.tex | 1 | ||||
-rw-r--r-- | src/preamble.tex | 55 | ||||
-rw-r--r-- | src/priv-csrs.tex | 1 | ||||
-rw-r--r-- | src/rv32.tex | 1 | ||||
-rw-r--r-- | src/rv64.tex | 2 |
5 files changed, 34 insertions, 26 deletions
@@ -129,7 +129,6 @@ occurs only when the most-negative integer is divided by $-1$. The quotient of a signed division with overflow is equal to the dividend, and the remainder is zero. Unsigned division overflow cannot occur. -\vspace{0.1in} \begin{table}[h] \center \begin{tabular}{|l|c|c||c|c|c|c|} diff --git a/src/preamble.tex b/src/preamble.tex index 5feba5a..1948407 100644 --- a/src/preamble.tex +++ b/src/preamble.tex @@ -61,34 +61,42 @@ {\end{tightlist}} \newenvironment{commentary} -{ \vspace{-0.2in} - \begin{quotation} - \noindent - \small \em - \rule{\linewidth}{1pt}\\ +{ \vspace{-1.5mm} + \list{}{ + \topsep 0mm + \partopsep 0mm + \listparindent 1.5em + \itemindent \listparindent + \rightmargin \leftmargin + \parsep 0mm + } + \item + \small\em + \noindent\nopagebreak\rule{\linewidth}{1pt}\par + \noindent\ignorespaces } -{ - \end{quotation} - \vspace{-0.2in} -} - +{\endlist} \newenvironment{samepage-commentary} {\begin{samepage} \begin{commentary}} {\end{commentary} \end{samepage}} -\newenvironment{discussion} -{ \vspace{-0.2in} - \begin{quotation} - \noindent - \small \em - \rule{\linewidth}{1pt} \\ - {\bf Discussion:} -} -{ - \end{quotation} - \vspace{-0.2in} -} +%\newenvironment{discussion} +%{ \vspace{-1.5mm} +% \list{}{ +% \topsep 0mm +% \partopsep 0mm +% \listparindent 1.5em +% \itemindent \listparindent +% \rightmargin \leftmargin +% \parsep 0mm +% } +% \item +% \small\em +% \noindent\nopagebreak\rule{\linewidth}{1pt}\par +% \noindent\textbf{Discussion:} +%} +%{\endlist} % Other commands and parameters @@ -96,6 +104,9 @@ \setlength{\parindent}{0in} \setlength{\parskip}{10pt} \sloppy +\raggedbottom +\clubpenalty=10000 +\widowpenalty=10000 % Commands for register format figures. diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index d38ea2c..03164cd 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -39,7 +39,6 @@ accesses to be intercepted. This change should be transparent to the less-privileged software. \end{commentary} -\vspace{0.2in} \begin{table*}[h!] \begin{center} \begin{tabular}{|c|c|c|c|l|} diff --git a/src/rv32.tex b/src/rv32.tex index a4bfd87..bbb2438 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -170,7 +170,6 @@ Other platforms may permit reserved opcode space be used for non-conforming extensions. \end{commentary} -\vspace{-0.2in} \begin{figure}[h] \begin{center} \setlength{\tabcolsep}{4pt} diff --git a/src/rv64.tex b/src/rv64.tex index 92a098a..9321ac4 100644 --- a/src/rv64.tex +++ b/src/rv64.tex @@ -65,7 +65,7 @@ ADDIW {\em rd, rs1, 0} writes the sign-extension of the lower 32 bits of register {\em rs1} into register {\em rd} (assembler pseudoinstruction SEXT.W). -\vspace{-0.2in} +\vspace{-0.4in} \begin{center} \begin{tabular}{R@{}W@{}R@{}R@{}R@{}R@{}O} \\ |