aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAndrew Waterman <andrew@sifive.com>2017-03-29 20:15:49 -0700
committerAndrew Waterman <andrew@sifive.com>2017-03-29 20:15:49 -0700
commit342140bd8db7f2a29cc94fbe1e61bfcb411a7155 (patch)
treeb43f00b2ff2a18d30dc09a5927f55ac66babe9e8
parentda6a19d33d6dc48d63059ce1f5b677dd919c3c14 (diff)
downloadriscv-isa-manual-342140bd8db7f2a29cc94fbe1e61bfcb411a7155.zip
riscv-isa-manual-342140bd8db7f2a29cc94fbe1e61bfcb411a7155.tar.gz
riscv-isa-manual-342140bd8db7f2a29cc94fbe1e61bfcb411a7155.tar.bz2
Clarify that misaligned accesses violating PMPs become partially visible
-rw-r--r--src/machine.tex14
1 files changed, 11 insertions, 3 deletions
diff --git a/src/machine.tex b/src/machine.tex
index bf661ec..e03c349 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -2657,6 +2657,14 @@ Failed accesses generate a load, store, or instruction access exception. Note
that a single instruction may generate multiple accesses, which may not be
mutually atomic. An access exception is generated if at least one access
generated by an instruction fails, though other accesses generated by that
-instruction may succeed with visible side effects. In particular, misaligned
-loads, stores, and instruction fetches may be decomposed into multiple
-accesses, as will instructions that reference virtual memory.
+instruction may succeed with visible side effects. In particular,
+instructions that reference virtual memory are decomposed into multiple
+accesses.
+
+On some implementations, misaligned loads, stores, and instruction fetches may
+also be decomposed into multiple accesses, some of which may succeed before an
+access exception is raised. Notably, the portion of a misaligned store that
+passes the PMP check may become visible, even if another portion fails the PMP
+check. The same behavior may manifest for floating-point stores wider than
+XLEN bits (e.g., the FSD instruction in RV32D), even when the store address is
+naturally aligned.