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authorAndrew Waterman <andrew@sifive.com>2020-02-28 18:12:47 -0800
committerAndrew Waterman <andrew@sifive.com>2020-02-28 18:12:47 -0800
commit27b40fbc798357fcb4b1deaba4553646fe677576 (patch)
treefbfa67054dbb4b3f9591f0ea063bd824ae11d107
parent6a1d35320da090788ac7206ed0a69f6937bf052d (diff)
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Clarify that FCVT instructions signal inexact
-rw-r--r--src/f.tex4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/f.tex b/src/f.tex
index 7680347..a9022c4 100644
--- a/src/f.tex
+++ b/src/f.tex
@@ -582,6 +582,10 @@ instructions round according to the {\em rm} field. A floating-point register
can be initialized to floating-point positive zero using FCVT.S.W {\em rd},
{\tt x0}, which will never set any exception flags.
+All floating-point conversion instructions raise the Inexact exception if the
+result differs from its operand value, yet is representable in the destination
+format.
+
\vspace{-0.2in}
\begin{center}
\begin{tabular}{R@{}F@{}R@{}R@{}F@{}R@{}O}