Expand sptbr.MODE field; don't spec Sv57/Sv64 for now

1 files changed, 23 insertions, 285 deletions

diff --git a/src/supervisor.tex b/src/supervisor.tex
index 7d3813e..74182cf 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -525,7 +525,7 @@ current address-translation scheme.
 \begin{figure}[h!]
 {\footnotesize
 \begin{center}
-\begin{tabular}{c@{}S@{}M}
+\begin{tabular}{c@{}E@{}K}
 \instbit{31} &
 \instbitrange{30}{22} &
 \instbitrange{21}{0} \\
@@ -551,24 +551,22 @@ a physical address space larger than \wunits{4}{GiB} for RV32.
 \begin{figure}[h!]
 {\footnotesize
 \begin{center}
-\begin{tabular}{@{}S@{}E@{}R@{}K}
-\instbitrange{63}{61} &
-\instbitrange{60}{45} &
-\instbitrange{44}{38} &
-\instbitrange{37}{0} \\
+\begin{tabular}{@{}S@{}T@{}U}
+\instbitrange{63}{60} &
+\instbitrange{59}{44} &
+\instbitrange{43}{0} \\
 \hline
 \multicolumn{1}{|c|}{{\tt MODE} (\warl)} &
 \multicolumn{1}{|c|}{{\tt ASID} (\warl)} &
-\multicolumn{1}{|c|}{0 (\wlrl)} &
 \multicolumn{1}{|c|}{{\tt PPN}  (\warl)} \\
 \hline
-3 & 16 & 7 & 38 \\
+4 & 16 & 44 \\
 \end{tabular}
 \end{center}
 }
 \vspace{-0.1in}
 \caption{RV64 Supervisor Page-Table Base Register {\tt sptbr}, for MODE
-values Sv39, Sv48, Sv57, and Sv64.}
+values Sv39 and Sv48.}
 \label{rv64ptbrreg}
 \end{figure}
 
@@ -590,11 +588,14 @@ have no effect.
 For RV32, the only other valid setting for MODE is Sv32, a paged
 virtual-memory scheme described in Section~\ref{sec:sv32}.
 
-For RV64, four paged virtual-memory schemes are defined: Sv39, Sv48, Sv57, and
-Sv64, described in Sections~\ref{sec:sv39}, \ref{sec:sv48}, \ref{sec:sv57},
-and \ref{sec:sv64}, respectively.  The remaining MODE settings are reserved
+For RV64, two paged virtual-memory schemes are defined: Sv39 and Sv48,
+described in Sections~\ref{sec:sv39} and \ref{sec:sv48}, respectively.
+Two additional schemes, Sv57 and Sv64, will be defined in a later version
+of this specification.  The remaining MODE settings are reserved
 for future use and may define different interpretations of the other fields in
-{\tt sptbr}.  Implementations are not required to support all MODE settings,
+{\tt sptbr}.
+
+Implementations are not required to support all MODE settings,
 and if {\tt sptbr} is written with an unsupported MODE, the entire write has
 no effect; no fields in {\tt sptbr} are modified.
 
@@ -614,11 +615,12 @@ Value  & Name & Description \\
 Value  & Name & Description \\
 \hline  
 0       & P     & No translation or protection. \\
-1--3    & ---   & {\em Reserved} \\
-4       & Sv39  & Page-based 39-bit virtual addressing. \\
-5       & Sv48  & Page-based 48-bit virtual addressing. \\
-6       & Sv57 &  Page-based 57-bit virtual addressing. \\
-7       & Sv64 &  Page-based 64-bit virtual addressing. \\
+1--7    & ---   & {\em Reserved} \\
+8       & Sv39  & Page-based 39-bit virtual addressing. \\
+9       & Sv48  & Page-based 48-bit virtual addressing. \\
+10      & {\em Sv57} & {\em Reserved for page-based 57-bit virtual addressing.} \\
+11      & {\em Sv64} & {\em Reserved for page-based 64-bit virtual addressing.} \\
+12--15  & ---   & {\em Reserved} \\
 \hline
 \end{tabular}
 \end{center}
@@ -1020,11 +1022,11 @@ design of Sv39 follows the overall scheme of Sv32, and this section
 details only the differences between the schemes.
 
 \begin{commentary}
-We specified four virtual memory systems for RV64 to relieve the tension
+We specified multiple virtual memory systems for RV64 to relieve the tension
 between providing a large address space and minimizing address-translation
 cost.  For many systems, \wunits{512}{GiB} of virtual-address space is ample,
-and so Sv39 suffices.  Sv48, Sv57, and Sv64 increase the virtual address space
-to terabytes, petabytes, and exabytes, but increase the physical memory
+and so Sv39 suffices.  Sv48 increases the virtual address space to
+\wunits{256}{TiB}, but increases the phyiscal memory
 capacity dedicated to page tables, the latency of page-table traversals, and
 the size of hardware structures that store virtual addresses.
 \end{commentary}
@@ -1285,267 +1287,3 @@ physically aligned to a boundary equal to its size.
 The algorithm for virtual-to-physical address translation is the same
 as in Section~\ref{sv32algorithm}, except LEVELS equals 4 and PTESIZE
 equals 8.
-
-\section{Sv57: Page-Based 57-bit Virtual-Memory System}
-\label{sec:sv57}
-
-This section describes a simple paged virtual-memory system designed for RV64
-systems, which supports 57-bit virtual address spaces.  It closely follows the
-design of Sv39 and Sv48, simply adding an additional level of page table to
-the latter, and so this chapter only details the differences between the two
-schemes.
-
-Implementations that support Sv57 should also support Sv39 and Sv48.
-
-\subsection{Addressing and Memory Protection}
-
-Sv57 implementations support a 57-bit virtual address space, divided
-into \wunits{4}{KiB} pages.  An Sv57 address is partitioned as
-shown in Figure~\ref{sv57va}.  Load and store effective addresses,
-which are 64 bits, must have bits 63--57 all equal to bit 56, or else
-an access fault will occur.  The 45-bit VPN is translated into a
-38-bit PPN via a four-level page table, while the 12-bit page offset
-is untranslated.
-
-\begin{figure*}[h!]
-{\footnotesize
-\begin{center}
-\begin{tabular}{@{}S@{}S@{}S@{}S@{}S@{}S}
-\instbitrange{56}{48} &
-\instbitrange{47}{39} &
-\instbitrange{38}{30} &
-\instbitrange{29}{21} &
-\instbitrange{20}{12} &
-\instbitrange{11}{0} \\
-\hline
-\multicolumn{1}{|c|}{VPN[4]} &
-\multicolumn{1}{c|}{VPN[3]} &
-\multicolumn{1}{c|}{VPN[2]} &
-\multicolumn{1}{c|}{VPN[1]} &
-\multicolumn{1}{c|}{VPN[0]} &
-\multicolumn{1}{c|}{page offset} \\
-\hline
-9 & 9 & 9 & 9 & 9 & 12 \\
-\end{tabular}
-\end{center}
-}
-\vspace{-0.1in}
-\caption{Sv57 virtual address.}
-\label{sv57va}
-\end{figure*}
-
-\begin{figure*}[h!]
-{\footnotesize
-\begin{center}
-\begin{tabular}{@{}F@{}S@{}S@{}S@{}S@{}S}
-\instbitrange{49}{48} &
-\instbitrange{47}{39} &
-\instbitrange{38}{30} &
-\instbitrange{29}{21} &
-\instbitrange{20}{12} &
-\instbitrange{11}{0} \\
-\hline
-\multicolumn{1}{|c|}{PPN[4]} &
-\multicolumn{1}{c|}{PPN[3]} &
-\multicolumn{1}{c|}{PPN[2]} &
-\multicolumn{1}{c|}{PPN[1]} &
-\multicolumn{1}{c|}{PPN[0]} &
-\multicolumn{1}{c|}{page offset} \\
-\hline
-2 & 9 & 9 & 9 & 9 & 12 \\
-\end{tabular}
-\end{center}
-}
-\vspace{-0.1in}
-\caption{Sv57 physical address.}
-\label{sv57pa}
-\end{figure*}
-
-\begin{figure*}[h!]
-{\footnotesize
-\begin{center}
-\begin{tabular}{@{}Y@{}F@{}F@{}F@{}F@{}F@{}Fcccccccc}
-\instbitrange{63}{48} &
-\instbitrange{47}{46} &
-\instbitrange{45}{37} &
-\instbitrange{36}{28} &
-\instbitrange{27}{19} &
-\instbitrange{18}{10} &
-\instbitrange{9}{8} &
-\instbit{7} &
-\instbit{6} &
-\instbit{5} &
-\instbit{4} &
-\instbit{3} &
-\instbit{2} &
-\instbit{1} &
-\instbit{0} \\
-\hline
-\multicolumn{1}{|c|}{\it Reserved} &
-\multicolumn{1}{c|}{PPN[4]} &
-\multicolumn{1}{c|}{PPN[3]} &
-\multicolumn{1}{c|}{PPN[2]} &
-\multicolumn{1}{c|}{PPN[1]} &
-\multicolumn{1}{c|}{PPN[0]} &
-\multicolumn{1}{c|}{RSW} &
-\multicolumn{1}{c|}{D} &
-\multicolumn{1}{c|}{A} &
-\multicolumn{1}{c|}{G} &
-\multicolumn{1}{c|}{U} &
-\multicolumn{1}{c|}{X} &
-\multicolumn{1}{c|}{W} &
-\multicolumn{1}{c|}{R} &
-\multicolumn{1}{c|}{V} \\
-\hline
-16 & 2 & 9 & 9 & 9 & 9 & 2 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1\\
-\end{tabular}
-\end{center}
-}
-\vspace{-0.1in}
-\caption{Sv57 page table entry.}
-\label{sv57pte}
-\end{figure*}
-
-The PTE format for Sv57 is shown in Figure~\ref{sv57pte}.  Bits 9--0
-have the same meaning as for Sv32.  Any level of PTE may be a leaf
-PTE, so in addition to \wunits{4}{KiB} pages, Sv57 supports
-\wunits{2}{MiB} {\em megapages}, \wunits{1}{GiB} {\em gigapages},
-\wunits{512}{GiB} {\em terapages}, and \wunits{256}{TiB} {\em petapages},
-each of which must be virtually and
-physically aligned to a boundary equal to its size.
-
-The algorithm for virtual-to-physical address translation is the same
-as in Section~\ref{sv32algorithm}, except LEVELS equals 5 and PTESIZE
-equals 8.
-
-\section{Sv64: Page-Based 64-bit Virtual-Memory System}
-\label{sec:sv64}
-
-This section describes a simple paged virtual-memory system designed for RV64
-systems, which supports 64-bit virtual address spaces.  It closely follows the
-design of Sv39, Sv48, and Sv57, simply adding an additional level of page table to
-the latter, and so this chapter only details the differences between the two
-schemes.
-
-Implementations that support Sv64 should also support Sv39, Sv48, and Sv57.
-
-\subsection{Addressing and Memory Protection}
-
-Sv64 implementations support a 64-bit virtual address space, divided
-into \wunits{4}{KiB} pages.  An Sv64 address is partitioned as
-shown in Figure~\ref{sv64va}.  The 52-bit VPN is translated into a
-38-bit PPN via a four-level page table, while the 12-bit page offset
-is untranslated.
-
-\begin{figure*}[h!]
-{\footnotesize
-\begin{center}
-\begin{tabular}{@{}Y@{}R@{}R@{}R@{}R@{}R@{}R}
-\instbitrange{63}{57} &
-\instbitrange{56}{48} &
-\instbitrange{47}{39} &
-\instbitrange{38}{30} &
-\instbitrange{29}{21} &
-\instbitrange{20}{12} &
-\instbitrange{11}{0} \\
-\hline
-\multicolumn{1}{|c|}{VPN[5]} &
-\multicolumn{1}{c|}{VPN[4]} &
-\multicolumn{1}{c|}{VPN[3]} &
-\multicolumn{1}{c|}{VPN[2]} &
-\multicolumn{1}{c|}{VPN[1]} &
-\multicolumn{1}{c|}{VPN[0]} &
-\multicolumn{1}{c|}{page offset} \\
-\hline
-7 & 9 & 9 & 9 & 9 & 9 & 12 \\
-\end{tabular}
-\end{center}
-}
-\vspace{-0.1in}
-\caption{Sv64 virtual address.}
-\label{sv64va}
-\end{figure*}
-
-\begin{figure*}[h!]
-{\footnotesize
-\begin{center}
-\begin{tabular}{@{}F@{}S@{}S@{}S@{}S@{}S}
-\instbitrange{49}{48} &
-\instbitrange{47}{39} &
-\instbitrange{38}{30} &
-\instbitrange{29}{21} &
-\instbitrange{20}{12} &
-\instbitrange{11}{0} \\
-\hline
-\multicolumn{1}{|c|}{PPN[4]} &
-\multicolumn{1}{c|}{PPN[3]} &
-\multicolumn{1}{c|}{PPN[2]} &
-\multicolumn{1}{c|}{PPN[1]} &
-\multicolumn{1}{c|}{PPN[0]} &
-\multicolumn{1}{c|}{page offset} \\
-\hline
-2 & 9 & 9 & 9 & 9 & 12 \\
-\end{tabular}
-\end{center}
-}
-\vspace{-0.1in}
-\caption{Sv64 physical address.}
-\label{sv64pa}
-\end{figure*}
-
-\begin{figure*}[h!]
-{\footnotesize
-\begin{center}
-\begin{tabular}{@{}F@{}F@{}F@{}F@{}F@{}F@{}Fcccccccc}
-\instbitrange{63}{48} &
-\instbitrange{47}{46} &
-\instbitrange{45}{37} &
-\instbitrange{36}{28} &
-\instbitrange{27}{19} &
-\instbitrange{18}{10} &
-\instbitrange{9}{8} &
-\instbit{7} &
-\instbit{6} &
-\instbit{5} &
-\instbit{4} &
-\instbit{3} &
-\instbit{2} &
-\instbit{1} &
-\instbit{0} \\
-\hline
-\multicolumn{1}{|c|}{\it Reserved} &
-\multicolumn{1}{c|}{PPN[4]} &
-\multicolumn{1}{c|}{PPN[3]} &
-\multicolumn{1}{c|}{PPN[2]} &
-\multicolumn{1}{c|}{PPN[1]} &
-\multicolumn{1}{c|}{PPN[0]} &
-\multicolumn{1}{c|}{RSW} &
-\multicolumn{1}{c|}{D} &
-\multicolumn{1}{c|}{A} &
-\multicolumn{1}{c|}{G} &
-\multicolumn{1}{c|}{U} &
-\multicolumn{1}{c|}{X} &
-\multicolumn{1}{c|}{W} &
-\multicolumn{1}{c|}{R} &
-\multicolumn{1}{c|}{V} \\
-\hline
-16 & 2 & 9 & 9 & 9 & 9 & 2 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1\\
-\end{tabular}
-\end{center}
-}
-\vspace{-0.1in}
-\caption{Sv64 page table entry.}
-\label{sv64pte}
-\end{figure*}
-
-The PTE format for Sv64 is shown in Figure~\ref{sv64pte}.  Bits 9--0
-have the same meaning as for Sv32.  Any level of PTE may be a leaf
-PTE, so in addition to \wunits{4}{KiB} pages, Sv64 supports
-\wunits{2}{MiB} {\em megapages}, \wunits{1}{GiB} {\em gigapages},
-\wunits{512}{GiB} {\em terapages}, \wunits{256}{TiB} {\em petapages},
-and \wunits{128}{PiB} {\em exapages}, each of which must be virtually and
-physically aligned to a boundary equal to its size.
-
-The algorithm for virtual-to-physical address translation is the same
-as in Section~\ref{sv32algorithm}, except LEVELS equals 6, PTESIZE
-equals 8, and PPN[5]=0.