diff options
author | Andrew Waterman <andrew@sifive.com> | 2017-04-11 19:32:01 -0700 |
---|---|---|
committer | Andrew Waterman <andrew@sifive.com> | 2017-04-11 19:32:01 -0700 |
commit | 15309edd9591084bdfaff7e9e076dc73c60262e0 (patch) | |
tree | fbe2efe46e6e098620129d7e0e2d819307962861 | |
parent | 59d33f6b833d6499edfa825a204933098345d53d (diff) | |
download | riscv-isa-manual-15309edd9591084bdfaff7e9e076dc73c60262e0.zip riscv-isa-manual-15309edd9591084bdfaff7e9e076dc73c60262e0.tar.gz riscv-isa-manual-15309edd9591084bdfaff7e9e076dc73c60262e0.tar.bz2 |
stval is optionally written with bad instruction, as with mtval
-rw-r--r-- | src/supervisor.tex | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 04104f4..0f03772 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -597,6 +597,20 @@ variable-length instructions, {\tt stval} will point to the portion of the instruction that caused the fault while {\tt sepc} will point to the beginning of the instruction. +The {\tt stval} register can optionally also be used to return the +faulting instruction bits on an illegal instruction exception ({\tt + sepc} points to the faulting instruction in memory). + +If this feature is not provided, then {\tt stval} is set to zero on +an illegal instruction fault. + +If the feature is provided, after an illegal instruction trap, {\tt + stval} will contain the entire faulting instruction provided the +instruction is no longer than XLEN bits. If the instruction is less +than XLEN bits long, the upper bits of {\tt stval} are cleared to +zero. If the instruction is more than XLEN bits long, {\tt stval} +will contain the first XLEN bits of the instruction. + \subsection{Supervisor Address Translation and Protection ({\tt satp}) Register} \label{sec:satp} |