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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2017-03-20 17:47:45 -0700 |
|---|---|---|
| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2017-03-20 17:47:45 -0700 |
| commit | 0162a2454bf8fb1bfaed907ba905415a24130c25 (patch) | |
| tree | 5dbd536effa647b87be317d005e292a3f7eebc7d | |
| parent | 2447f7421b0f4cae96b54774fc65c5e535e3888e (diff) | |
| download | riscv-isa-manual-0162a2454bf8fb1bfaed907ba905415a24130c25.zip riscv-isa-manual-0162a2454bf8fb1bfaed907ba905415a24130c25.tar.gz riscv-isa-manual-0162a2454bf8fb1bfaed907ba905415a24130c25.tar.bz2 | |
Small changes.
| -rw-r--r-- | src/machine.tex | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/machine.tex b/src/machine.tex index 8249a1a..96f8e2a 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -19,7 +19,7 @@ M-mode code can access all CSRs at lower privilege levels. \subsection{Machine ISA Register {\tt misa}} -The {\tt misa} register is an XLEN-bit \warl\ read-write register +The {\tt misa} CSR is an XLEN-bit \warl\ read-write register reporting the ISA supported by the hart. This register must be readable in any implementation, but a value of zero can be returned to indicate the {\tt misa} register has not been implemented, requiring @@ -90,7 +90,7 @@ The ``G'' bit is used as an escape to allow expansion to a larger space of standard extension names. \begin{commentary} G is used to indicate the combination IMAFD, so is redundant in the -{\tt misa} register, hence we reserve the bit to indicate that +{\tt misa} CSR, hence we reserve the bit to indicate that additional standard extensions are present. \end{commentary} @@ -141,7 +141,7 @@ Bit & Character & Description \\ \begin{commentary} -The {\tt misa} register exposes a rudimentary catalog of CPU features +The {\tt misa} CSR exposes a rudimentary catalog of CPU features to machine-mode code. More extensive information can be obtained in machine mode by probing other machine registers, and examining other ROM storage in the system as part of the boot process. @@ -283,14 +283,14 @@ XLEN \\ The format of this field is left to the provider of the architecture source code, but will be often be printed by standard tools as a hexadecimal string without any leading or trailing zeros, so the -Implementation value should be left-justified (i.e., filled in from +Implementation value can be left-justified (i.e., filled in from most-significant nibble down) with subfields aligned on nibble boundaries to ease human readability. \end{commentary} \subsection{Hart ID Register {\tt mhartid}} -The {\tt mhartid} register is an XLEN-bit read-only register +The {\tt mhartid} CSR is an XLEN-bit read-only register containing the integer ID of the hardware thread running the code. This register must be readable in any implementation. Hart IDs might not necessarily be numbered contiguously in a multiprocessor system, |