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| author | Andrew Waterman <andrew@sifive.com> | 2020-05-05 13:55:08 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-05-05 13:55:08 -0700 |
| commit | 009841616c6145fdf5cd9ccfaf9d3692f0bf9f80 (patch) | |
| tree | 99d5a45adddc58490b24d1ad55acf82414a69392 | |
| parent | 0e6e1d4f440116d604356f5b4aa04765f9663502 (diff) | |
| download | riscv-isa-manual-009841616c6145fdf5cd9ccfaf9d3692f0bf9f80.zip riscv-isa-manual-009841616c6145fdf5cd9ccfaf9d3692f0bf9f80.tar.gz riscv-isa-manual-009841616c6145fdf5cd9ccfaf9d3692f0bf9f80.tar.bz2 | |
Clarify that _coherent_ main memory regions use RVWMO or RVTSO
| -rw-r--r-- | src/machine.tex | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index 2a14451..94c58f4 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2814,8 +2814,10 @@ instruction and atomic-instruction ordering bits. Accesses by one hart to main memory regions are observable not only by other harts but also by other devices with the capability to initiate -requests in the main memory system (e.g., DMA engines). Main memory -regions always have either the RVWMO or RVTSO memory model. +requests in the main memory system (e.g., DMA engines). +Coherent main memory regions always have either the RVWMO or RVTSO memory +model. +Incoherent main memory regions have an implementation-defined memory model. Accesses by one hart to an I/O region are observable not only by other harts and bus mastering devices but also by targeted slave I/O devices, and I/O |