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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-30 02:14:45 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-30 02:14:45 -0700 |
| commit | 001e1adac0730370611ea337784c0f234846e0ec (patch) | |
| tree | cdd33696609dc71ffc53a8a6fffd6c0ecd43b5d6 | |
| parent | 342140bd8db7f2a29cc94fbe1e61bfcb411a7155 (diff) | |
| download | riscv-isa-manual-001e1adac0730370611ea337784c0f234846e0ec.zip riscv-isa-manual-001e1adac0730370611ea337784c0f234846e0ec.tar.gz riscv-isa-manual-001e1adac0730370611ea337784c0f234846e0ec.tar.bz2 | |
PMP cleanup
| -rw-r--r-- | src/machine.tex | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/src/machine.tex b/src/machine.tex index e03c349..67947e8 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2305,8 +2305,8 @@ issue misaligned accesses to non-idempotent regions. To support secure processing and contain faults, it is desirable to limit the physical addresses accessible by software running on a hart. -A physical memory protection (PMP) unit can be -provided, with per-hart machine-mode control registers to allow +An optional physical memory protection (PMP) unit provides +per-hart machine-mode control registers to allow physical memory access privileges (read, write, execute) to be specified for each physical memory region. The PMP values are checked in parallel with the PMA checks described in Section~\ref{sec:pma}. @@ -2338,13 +2338,15 @@ reset. PMP violations are always trapped precisely at the processor. PMP entries are described by an 8-bit configuration register and one XLEN-bit address register. Some PMP settings additionally use the address register associated with the preceding PMP entry. Up to 16 PMP entries are supported. +If any PMP entries are implemented, then all PMP CSRs must be implemented, +but all PMP CSR fields are \warl\ and may be hardwired to zero. The PMP configuration registers are densely packed into CSRs to minimize -context-switch time. For RV32, four CSRs, {\tt pmpcfg0}--{\tt pmpcfg3}, +context-switch time. For RV32, four CSRs, {\tt pmpcfg0}--{\tt pmpcfg3}, hold +the configurations {\tt pmp0cfg}--{\tt pmp15cfg} for the 16 PMP entries, as +shown in Figure~\ref{pmpcfg-rv32}. For RV64, {\tt pmpcfg0} and {\tt pmpcfg2} hold the configurations for the 16 PMP entries, as shown in -Figure~\ref{pmpcfg-rv32}. For RV64, {\tt pmpcfg0} and {\tt pmpcfg2} hold -the configurations for the 16 PMP entries, as shown in -Figure~\ref{pmpcfg-rv64}. +Figure~\ref{pmpcfg-rv64}, and {\tt pmpcfg1} and {\tt pmpcfg3} are illegal. \begin{commentary} RV64 systems use {\tt pmpcfg2}, rather than {\tt pmpcfg1}, to hold |