More work on HINTs

3 files changed, 121 insertions, 24 deletions

diff --git a/src/c.tex b/src/c.tex
index 0b47699..dcb22c3 100644
--- a/src/c.tex
+++ b/src/c.tex
@@ -1138,6 +1138,63 @@ the A and C extensions must ensure that LR/SC sequences containing
 valid C instructions will eventually complete.
 \end{commentary}
 
+\section{HINT Instructions}
+\label{sec:rvc-hints}
+
+A portion of the RVC encoding space is reserved for microarchitectural HINTs.
+Like the HINTs in the RV32I base ISA (see Section~\ref{sec:rv32i-hints}),
+these instructions do not modify any architectural state, except for advancing
+the {\tt pc} and the instructions-retired counter {\tt instret}.  HINTs are
+executed as no-ops on implementations that ignore them.
+
+RVC HINTs are encoded as computational instructions that do not modify the
+architectural state, either because {\em rd}={\tt x0}
+(e.g. \mbox{C.ADD {\em x0}, {\em t0}}), or because {\em rd} is overwritten
+with a copy of itself (e.g. \mbox{C.ADDI {\em t0}, 0}).
+
+\begin{commentary}
+This HINT encoding has been chosen so that simple implementations can ignore
+HINTs altogether, and instead execute a HINT as a regular computational
+instruction that happens not to mutate the architectural state.
+\end{commentary}
+
+RVC HINTs do not necessarily expand to their RVI HINT counterparts.  For
+example, \mbox{C.ADD {\em x0}, {\em t0}} might not encode the same HINT
+as \mbox{ADD {\em x0}, {\em x0}, {\em t0}}.
+
+\begin{commentary}
+We expect the static and dynamic frequency of HINT code points will vary
+dramatically.  Decoupling the RVC and RVI HINT mappings allows the scarce RVC
+HINT space to be allocated to the most popular HINTs.
+\end{commentary}
+
+Table~\ref{tab:rvc-hints} lists all RVC HINT code points.  For RV32C, 78\% of
+the HINT space is reserved for standard HINTs, but none are presently defined.
+The remainder of the HINT space is reserved for custom HINTs: no standard
+HINTs will ever be defined in this subspace.
+
+\begin{table}[hbt]
+\centering
+\begin{tabular}{|l|l|r|l|}
+  \hline
+  Instruction             & Constraints                                 & Code Points & Purpose \\ \hline \hline
+  C.NOP                   & {\em nzimm}$\neq$0                          & 63          & \multirow{6}{*}{\em Reserved for future standard use} \\ \cline{1-3}
+  C.ADDI                  & {\em rd}$\neq${\tt x0}, {\em nzimm}=0       & 31          & \\ \cline{1-3}
+  C.LI                    & {\em rd}={\tt x0}                           & 64          & \\ \cline{1-3}
+  C.LUI                   & {\em rd}={\tt x0}, {\em nzimm}$\neq$0       & 63          & \\ \cline{1-3}
+  C.MV                    & {\em rd}={\tt x0}, {\em rs2}$\neq${\tt x0}  & 31          & \\ \cline{1-3}
+  C.ADD                   & {\em rd}={\tt x0}, {\em rs2}$\neq${\tt x0}  & 31          & \\ \hline \hline
+  \multirow{2}{*}{C.SLLI} & \multirow{2}{*}{{\em rd}={\tt x0}, {\em nzimm}$\neq$0} & 31 (RV32)   & \multirow{6}{*}{\em Reserved for custom use} \\
+                          &                                             & 63 (RV64/128) & \\ \cline{1-3}
+  C.SLLI64                & {\em rd}={\tt x0}                           & 1           & \\ \cline{1-3}
+  C.SLLI64                & {\em rd}$\neq${\tt x0}, RV32 and RV64 only  & 31          & \\ \cline{1-3}
+  C.SRLI64                & RV32 and RV64 only                          & 8           & \\ \cline{1-3}
+  C.SRAI64                & RV32 and RV64 only                          & 8           & \\ \hline
+\end{tabular}
+\caption{RVC HINT instructions.}
+\label{tab:rvc-hints}
+\end{table}
+
 \clearpage
 
 \section{RVC Instruction Set Listings}
@@ -1149,21 +1206,7 @@ are only valid for certain operands; when invalid, they are marked
 either {\em RES} to indicate that the opcode is reserved for future
 standard extensions; {\em NSE} to indicate that the opcode is reserved
 for non-standard extensions; or {\em HINT} to indicate that the opcode
-is reserved for future standard microarchitectural hints.
-Instructions marked {\em HINT} must execute as no-ops on
-implementations for which the hint has no effect.
-
-\begin{commentary}
-The HINT instructions are designed to support future addition of
-microarchitectural hints that might affect performance but cannot
-affect architectural state.  The HINT encodings have been chosen so
-that simple implementations can ignore the HINT encoding and execute
-the HINT as a regular operation that does not change architectural
-state.  For example, C.ADD is a HINT if the destination register is
-{\tt x0}, where the five-bit rs2 field encodes details of the HINT.
-However, a simple implementation can simply execute the HINT as an add
-to register {\tt x0}, which will have no effect.
-\end{commentary}
+is reserved for microarchitectural hints (see Section~\ref{sec:rvc-hints}).
 
 \input{rvc-opcode-map}
 
diff --git a/src/rv32.tex b/src/rv32.tex
index dce869e..8944e2d 100644
--- a/src/rv32.tex
+++ b/src/rv32.tex
@@ -1534,8 +1534,8 @@ Implementations are always allowed to ignore HINTs.
 
 \begin{commentary}
 This HINT encoding has been chosen so that simple implementations can ignore
-HINTs altogether, and instead execute the HINT as a regular computational
-instruction that does not change the architectural state.  For example, ADD is
+HINTs altogether, and instead execute a HINT as a regular computational
+instruction that happens not to mutate the architectural state.  For example, ADD is
 a HINT if the destination register is {\tt x0}; the five-bit {\em rs1} and {\em
 rs2} fields encode arguments to the HINT.  However, a simple implementation can
 simply execute the HINT as an ADD of {\em rs1} and {\em rs2} that writes {\tt
@@ -1557,17 +1557,14 @@ standardized.
 \centering
 \begin{tabular}{|l|l|c|l|}
   \hline
-  Instruction           & Constraints                                 & Code Points & Meaning \\ \hline
-  LUI                   & {\em rd}={\tt x0}                           & $2^{20}$                    & \multirow{18}{*}{\em Reserved for future standard use} \\ \cline{1-3}
+  Instruction           & Constraints                                 & Code Points & Purpose \\ \hline \hline
+  LUI                   & {\em rd}={\tt x0}                           & $2^{20}$                    & \multirow{15}{*}{\em Reserved for future standard use} \\ \cline{1-3}
   AUIPC                 & {\em rd}={\tt x0}                           & $2^{20}$                    & \\ \cline{1-3}
   \multirow{2}{*}{ADDI} & {\em rd}={\tt x0}, and either               & \multirow{2}{*}{$2^{17}-1$} & \\
                         & {\em rs1}$\neq${\tt x0} or {\em imm}$\neq$0 &                             & \\ \cline{1-3}
   ANDI                  & {\em rd}={\tt x0}                           & $2^{17}$                    & \\ \cline{1-3}
   ORI                   & {\em rd}={\tt x0}                           & $2^{17}$                    & \\ \cline{1-3}
   XORI                  & {\em rd}={\tt x0}                           & $2^{17}$                    & \\ \cline{1-3}
-  SLLI                  & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
-  SRLI                  & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
-  SRAI                  & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
   ADD                   & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
   SUB                   & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
   AND                   & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
@@ -1575,9 +1572,12 @@ standardized.
   XOR                   & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
   SLL                   & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
   SRL                   & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
-  SRA                   & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \hline
-  SLTI                  & {\em rd}={\tt x0}                           & $2^{17}$                    & \multirow{4}{*}{\em Reserved for custom use} \\ \cline{1-3}
+  SRA                   & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \hline \hline
+  SLTI                  & {\em rd}={\tt x0}                           & $2^{17}$                    & \multirow{7}{*}{\em Reserved for custom use} \\ \cline{1-3}
   SLTIU                 & {\em rd}={\tt x0}                           & $2^{17}$                    & \\ \cline{1-3}
+  SLLI                  & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
+  SRLI                  & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
+  SRAI                  & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
   SLT                   & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
   SLTU                  & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \hline
 \end{tabular}
diff --git a/src/rv64.tex b/src/rv64.tex
index df5db20..bac88cb 100644
--- a/src/rv64.tex
+++ b/src/rv64.tex
@@ -251,3 +251,57 @@ RDCYCLE, RDTIME, and RDINSTRET pseudoinstructions read the full 64 bits of
 the {\tt cycle}, {\tt time}, and {\tt instret} counters.  Hence, the RDCYCLEH,
 RDTIMEH, and RDINSTRETH instructions are not necessary and are illegal in
 RV64I.
+
+\section{HINT Instructions}
+\label{sec:rv64i-hints}
+
+All instructions that are microarchitectural HINTs in RV32I (see
+Section~\ref{sec:rv32i-hints}) are also HINTs in RV64I.  The
+additional computational instructions in RV64I expand both the standard and
+custom HINT encoding spaces.
+
+Table~\ref{tab:rv64i-hints} lists all RV64I HINT code points.  91\% of the HINT
+space is reserved for standard HINTs, but none are presently defined.  The
+remainder of the HINT space is reserved for custom HINTs: no standard HINTs
+will ever be defined in this subspace.
+
+\begin{table}[hbt]
+\centering
+\begin{tabular}{|l|l|c|l|}
+  \hline
+  Instruction           & Constraints                                 & Code Points & Purpose \\ \hline \hline
+  LUI                   & {\em rd}={\tt x0}                           & $2^{20}$                    & \multirow{21}{*}{\em Reserved for future standard use} \\ \cline{1-3}
+  AUIPC                 & {\em rd}={\tt x0}                           & $2^{20}$                    & \\ \cline{1-3}
+  \multirow{2}{*}{ADDI} & {\em rd}={\tt x0}, and either               & \multirow{2}{*}{$2^{17}-1$} & \\
+                        & {\em rs1}$\neq${\tt x0} or {\em imm}$\neq$0 &                             & \\ \cline{1-3}
+  ANDI                  & {\em rd}={\tt x0}                           & $2^{17}$                    & \\ \cline{1-3}
+  ORI                   & {\em rd}={\tt x0}                           & $2^{17}$                    & \\ \cline{1-3}
+  XORI                  & {\em rd}={\tt x0}                           & $2^{17}$                    & \\ \cline{1-3}
+  ADDIW                 & {\em rd}={\tt x0}                           & $2^{17}$                    & \\ \cline{1-3}
+  ADD                   & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
+  SUB                   & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
+  AND                   & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
+  OR                    & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
+  XOR                   & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
+  SLL                   & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
+  SRL                   & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
+  SRA                   & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
+  ADDW                  & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
+  SUBW                  & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
+  SLLW                  & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
+  SRLW                  & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
+  SRAW                  & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \hline \hline
+  SLTI                  & {\em rd}={\tt x0}                           & $2^{17}$                    & \multirow{10}{*}{\em Reserved for custom use} \\ \cline{1-3}
+  SLTIU                 & {\em rd}={\tt x0}                           & $2^{17}$                    & \\ \cline{1-3}
+  SLLI                  & {\em rd}={\tt x0}                           & $2^{11}$                    & \\ \cline{1-3}
+  SRLI                  & {\em rd}={\tt x0}                           & $2^{11}$                    & \\ \cline{1-3}
+  SRAI                  & {\em rd}={\tt x0}                           & $2^{11}$                    & \\ \cline{1-3}
+  SLLIW                 & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
+  SRLIW                 & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
+  SRAIW                 & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
+  SLT                   & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \cline{1-3}
+  SLTU                  & {\em rd}={\tt x0}                           & $2^{10}$                    & \\ \hline
+\end{tabular}
+\caption{RV64I HINT instructions.}
+\label{tab:rv64i-hints}
+\end{table}