Allow access exceptions to be reported on misaligned atomic memory operations where they should not be emulated.

2 files changed, 20 insertions, 10 deletions

diff --git a/src/a.tex b/src/a.tex
index 550dd53..a1e88b3 100644
--- a/src/a.tex
+++ b/src/a.tex
@@ -132,10 +132,14 @@ for the SLT/SLTU instructions.  More specific failure codes might be
 defined in future versions or extensions to the ISA.
 \end{commentary}
 
-For LR and SC, the A extension requires that the address held in {\em rs1} be
-naturally aligned to the size of the operand (i.e., eight-byte aligned for
-64-bit words and four-byte aligned for 32-bit words).  If the address is
-not naturally aligned, a misaligned address exception will be generated.
+For LR and SC, the A extension requires that the address held in {\em
+  rs1} be naturally aligned to the size of the operand (i.e.,
+eight-byte aligned for 64-bit words and four-byte aligned for 32-bit
+words).  If the address is not naturally aligned, a misaligned address
+exception or an access exception will be generated.  The access
+exception can be generated for a memory access that would otherwise be
+able to complete except for the misalignment, if the misaligned access
+should not be emulated.
 
 \label{lrscseq}
 
@@ -311,12 +315,16 @@ to the address in {\em rs1}. AMOs can either operate on 64-bit (RV64
 only) or 32-bit words in memory.  For RV64, 32-bit AMOs always
 sign-extend the value placed in {\em rd}.
 
-For AMOs, the A extension requires that the address held in {\em rs1} be
-naturally aligned to the size of the operand (i.e., eight-byte aligned for
-64-bit words and four-byte aligned for 32-bit words).  If the address is
-not naturally aligned, a misaligned address exception will be generated.
-The ``Zam'' extension, described in Chapter~\ref{sec:zam}, relaxes this
-requirement and specifies the semantics of misaligned AMOs.
+For AMOs, the A extension requires that the address held in {\em rs1}
+be naturally aligned to the size of the operand (i.e., eight-byte
+aligned for 64-bit words and four-byte aligned for 32-bit words).  If
+the address is not naturally aligned, a misaligned address exception
+or an access exception will be generated.  The access exception can be
+generated for a memory access that would otherwise be able to complete
+except for the misalignment, if the misaligned access should not be
+emulated.  The ``Zam'' extension, described in Chapter~\ref{sec:zam},
+relaxes this requirement and specifies the semantics of misaligned
+AMOs.
 
 The operations supported are swap, integer add, logical AND, logical
 OR, logical XOR, and signed and unsigned integer maximum and minimum.
diff --git a/src/preface.tex b/src/preface.tex
index 8abdb45..140df7e 100644
--- a/src/preface.tex
+++ b/src/preface.tex
@@ -84,6 +84,8 @@ The major changes in this version of the document include:
   This behavior was already needed to support the definition of the
   classic privileged architecture.  Also, now allow access exceptions
   to be reported for misaligned access that should not be emulated.
+  The same ability to report access exceptions instead of misaligned
+  exceptions was added for atomic operations also.
 \item Moved FENCE.I out of the mandatory base and into a separate extension,
   with Zifencei ISA name.  FENCE.I was removed from the Linux user ABI and is
   problematic in implementations with large incoherent instruction and