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| author | Andrew Waterman <andrew@sifive.com> | 2019-03-14 20:27:04 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-03-14 20:27:04 -0700 |
| commit | c8c3a436efabcc050738c8fa7414620f6637578a (patch) | |
| tree | ed7157e1200854029187dc5a6624579fc06894c6 | |
| parent | bf8dbdb2a747fa3d6b4ff6540a4fb31af556568b (diff) | |
| download | riscv-isa-manual-c8c3a436efabcc050738c8fa7414620f6637578a.zip riscv-isa-manual-c8c3a436efabcc050738c8fa7414620f6637578a.tar.gz riscv-isa-manual-c8c3a436efabcc050738c8fa7414620f6637578a.tar.bz2 | |
memory -> main memory
| -rw-r--r-- | src/csr.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/csr.tex b/src/csr.tex index f73a8cd..16d8e6f 100644 --- a/src/csr.tex +++ b/src/csr.tex @@ -182,7 +182,7 @@ scheme. \begin{commentary} These CSR-ordering constraints are imposed primarily to support ordering -memory and memory-mapped I/O accesses with respect to reads of the {\tt time} +main memory and memory-mapped I/O accesses with respect to reads of the {\tt time} CSR. With the exception of the {\tt time}, {\tt cycle}, and {\tt mcycle} CSRs, the CSRs defined thus far in Volumes I and II of this specification are not directly accessible to other harts or devices and cause no side effects |