Don't hyphenate "sign extension" when used as noun

6 files changed, 12 insertions, 12 deletions

diff --git a/src/b-st-ext.adoc b/src/b-st-ext.adoc
index 21cded7..a0b5e34 100644
--- a/src/b-st-ext.adoc
+++ b/src/b-st-ext.adoc
@@ -639,11 +639,11 @@ instructions that return the smaller/larger of two operands.
 |<<#insns-minu>>
 |===
 
-===== Sign- and zero-extension
+===== Sign extension and zero extension
 
-These instructions perform the sign-extension or zero-extension of the least significant 8 bits or 16 bits of the source register.
+These instructions perform the sign extension or zero extension of the least significant 8 bits or 16 bits of the source register.
 
-These instructions replace the generalized idioms `slli rD,rS,(XLEN-<size>) + srli` (for zero-extension) or `slli + srai` (for sign-extension) for the sign-extension of 8-bit and 16-bit quantities, and for the zero-extension of 16-bit quantities.
+These instructions replace the generalized idioms `slli rD,rS,(XLEN-<size>) + srli` (for zero extension) or `slli + srai` (for sign extension) for the sign extension of 8-bit and 16-bit quantities, and for the zero extension of 16-bit quantities.
 
 [%header,cols="^1,^1,4,8"]
 |===
diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc
index b4fe138..97aca5f 100644
--- a/src/c-st-ext.adoc
+++ b/src/c-st-ext.adoc
@@ -202,7 +202,7 @@ The formats were designed to keep bits for the two register source
 specifiers in the same place in all instructions, while the destination
 register field can move. When the full 5-bit destination register
 specifier is present, it is in the same place as in the 32-bit RISC-V
-encoding. Where immediates are sign-extended, the sign-extension is
+encoding. Where immediates are sign-extended, the sign extension is
 always from bit 12. Immediate fields have been scrambled, as in the base
 specification, to reduce the number of immediate muxes required.
 [NOTE]
diff --git a/src/m-st-ext.adoc b/src/m-st-ext.adoc
index 5f3c7de..fc08be2 100644
--- a/src/m-st-ext.adoc
+++ b/src/m-st-ext.adoc
@@ -38,7 +38,7 @@ with the less-significant words of the multiplier (which are unsigned).
 ====
 
 MULW is an RV64 instruction that multiplies the lower 32 bits of the
-source registers, placing the sign-extension of the lower 32 bits of the
+source registers, placing the sign extension of the lower 32 bits of the
 result into the destination register.
 
 [NOTE]
diff --git a/src/rv32.adoc b/src/rv32.adoc
index bd38ac8..9714df4 100644
--- a/src/rv32.adoc
+++ b/src/rv32.adoc
@@ -192,7 +192,7 @@ plus a special load-upper-immediate instruction with 20 bits) to
 increase the opcode space available for regular instructions.
 
 Immediates are sign-extended because we did not observe a benefit to
-using zero-extension for some immediates as in the MIPS ISA and wanted
+using zero extension for some immediates as in the MIPS ISA and wanted
 to keep the ISA as simple as possible.
 ====
 
@@ -230,10 +230,10 @@ The fields are labeled with the instruction bits used to construct their value.
 
 [NOTE]
 ====
-Sign-extension is one of the most critical operations on immediates
+Sign extension is one of the most critical operations on immediates
 (particularly for XLEN>32), and in RISC-V the sign bit for
 all immediates is always held in bit 31 of the instruction to allow
-sign-extension to proceed in parallel with instruction decoding.
+sign extension to proceed in parallel with instruction decoding.
 
 Although more complex implementations might have separate adders for
 branch and jump calculations and so would not benefit from keeping the
diff --git a/src/rv64.adoc b/src/rv64.adoc
index b675dc1..531158a 100644
--- a/src/rv64.adoc
+++ b/src/rv64.adoc
@@ -44,10 +44,10 @@ include::images/wavedrom/rv64i-base-int.adoc[]
 //.RV64I register-immediate instructions
 
 ADDIW is an RV64I instruction that adds the sign-extended 12-bit
-immediate to register _rs1_ and produces the proper sign-extension of a
+immediate to register _rs1_ and produces the proper sign extension of a
 32-bit result in _rd_. Overflows are ignored and the result is the low
 32 bits of the result sign-extended to 64 bits. Note, ADDIW _rd, rs1, 0_
-writes the sign-extension of the lower 32 bits of register _rs1_ into
+writes the sign extension of the lower 32 bits of register _rs1_ into
 register _rd_ (assembler pseudoinstruction SEXT.W).
 
 include::images/wavedrom/rv64i-slli.adoc[]
diff --git a/src/supervisor.adoc b/src/supervisor.adoc
index 3304257..3e72893 100644
--- a/src/supervisor.adoc
+++ b/src/supervisor.adoc
@@ -1113,7 +1113,7 @@ physical address bits found in the implementation.
 ====
 For example, consider an RV32 system supporting 34 bits of physical
 address. When the value of `satp`.MODE is Sv32, a 34-bit physical
-address is produced directly, and therefore no zero-extension is needed.
+address is produced directly, and therefore no zero extension is needed.
 When the value of `satp`.MODE is Bare, the 32-bit virtual address is
 translated (unmodified) into a 32-bit physical address, and then that
 physical address is zero-extended into a 34-bit machine-level physical
@@ -1509,7 +1509,7 @@ the 12-bit page offset is untranslated.
 When mapping between narrower and wider addresses, RISC-V zero-extends a
 narrower physical address to a wider size. The mapping between 64-bit
 virtual addresses and the 39-bit usable address space of Sv39 is not
-based on zero-extension but instead follows an entrenched convention
+based on zero extension but instead follows an entrenched convention
 that allows an OS to use one or a few of the most-significant bits of a
 full-size (64-bit) virtual address to quickly distinguish user and
 supervisor address regions.