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| author | Andrew Waterman <andrew@sifive.com> | 2019-03-28 01:48:19 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-03-28 01:48:19 -0700 |
| commit | b8e008d435b5a5bd004cf1605e39de6d915bbafd (patch) | |
| tree | 37ec80c56cdc50f3e5d555092dd6f693af01948f | |
| parent | c61540b154184452f1e9420c05e983c04157bede (diff) | |
| download | riscv-isa-manual-b8e008d435b5a5bd004cf1605e39de6d915bbafd.zip riscv-isa-manual-b8e008d435b5a5bd004cf1605e39de6d915bbafd.tar.gz riscv-isa-manual-b8e008d435b5a5bd004cf1605e39de6d915bbafd.tar.bz2 | |
mhpmcounters are WARL
We inadvertently excised commentary that mentioned this possibility
in 8e52ffa49d09437c69fec6e173dfbddeb9e8ea1a.
Thanks to @ccelio for pointing this out.
| -rw-r--r-- | src/machine.tex | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index b44cf75..617b43a 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1587,7 +1587,13 @@ both the counter and its corresponding event selector to 0. \caption{Hardware performance monitor counters.} \end{figure} -All of these counters have 64-bit precision on RV32 and RV64. +The {\tt mhpmcounter}s are \warl\ registers that support up to 64 bits of +precision on RV32 and RV64. + +\begin{commentary} +A future revision of this specification will define a mechanism to generate an +interrupt when a hardware performance monitor counter overflows. +\end{commentary} On RV32 only, reads of the {\tt mcycle}, {\tt minstret}, and {\tt mhpmcounter{\em n}} CSRs return the low 32 bits, while reads of the {\tt |