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| author | wmat <wmat@riscv.org> | 2024-05-08 11:09:38 -0400 |
|---|---|---|
| committer | wmat <wmat@riscv.org> | 2024-05-08 11:09:38 -0400 |
| commit | aab233c2a46ad0f560617562305bf2d2283712d0 (patch) | |
| tree | 4bb0193fe5e6fb42e49e82d5f50b13e05d9173c1 | |
| parent | 52382504bab08c2c0363fe1dfab8a91e514fc108 (diff) | |
| download | riscv-isa-manual-aab233c2a46ad0f560617562305bf2d2283712d0.zip riscv-isa-manual-aab233c2a46ad0f560617562305bf2d2283712d0.tar.gz riscv-isa-manual-aab233c2a46ad0f560617562305bf2d2283712d0.tar.bz2 | |
Applying alasdairs fixes
Applying alasdairs fixes
| -rw-r--r-- | src/c-st-ext.adoc | 1 | ||||
| -rw-r--r-- | src/rv64.adoc | 4 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc index bd33ef9..dcf4ca6 100644 --- a/src/c-st-ext.adoc +++ b/src/c-st-ext.adoc @@ -311,6 +311,7 @@ only valid when _rd_≠x0 the code points with _rd_=x0 are reserved. C.LWSP SAIL Code: //include::sail:execute[part=body,unindent,clause="RISCV_C_LWSP(_, _)"] +sail::execute[clause="C_LWSP(_, _)",part=body,unindent] C.LDSP is an RV64C/RV128C-only instruction that loads a 64-bit value from memory into register _rd_. It computes its effective address by diff --git a/src/rv64.adoc b/src/rv64.adoc index 23af78e..816594d 100644 --- a/src/rv64.adoc +++ b/src/rv64.adoc @@ -73,7 +73,7 @@ copied into the vacated upper bits). (((RV64I, SRLIW))) (((RV64I, RV64I-only))) -include::sail:execute[part=body,dedent,clause="SHIFTIOP(_,_,_,_)"] +sail::execute[part=body,dedent,clause="SHIFTIOP(_,_,_,_)"] include::images/wavedrom/rv64i-slliw.adoc[] [[rv64i-slliw]] @@ -83,7 +83,7 @@ defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. SLLIW, SRLIW, and SRAIW encodings with _imm[5] ≠ 0_ are reserved. -include::sail:execute[part=body,dedent,clause="ADDIW(_,_,_)"] +sail::execute[part=body,dedent,clause="SHIFTIWOP(_,_,_,_)"] [NOTE] |