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author | Andrew Waterman <andrew@sifive.com> | 2019-04-19 19:24:45 -0500 |
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committer | Andrew Waterman <andrew@sifive.com> | 2019-04-19 19:24:45 -0500 |
commit | aa5734d69383c97c119923d1e823997e3e2930c5 (patch) | |
tree | 0e7672e8e43c0d7313ae6f327ec4dfbb0d8eecb2 | |
parent | 74ad5311d7263a915574dfa04ab28dffab34afcd (diff) | |
download | riscv-isa-manual-aa5734d69383c97c119923d1e823997e3e2930c5.zip riscv-isa-manual-aa5734d69383c97c119923d1e823997e3e2930c5.tar.gz riscv-isa-manual-aa5734d69383c97c119923d1e823997e3e2930c5.tar.bz2 |
Remove outdated clause indicating incorrect exception priorities
The clause was superseded by Table 3.7, but we failed to delete it.
Closes #372
-rw-r--r-- | src/supervisor.tex | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 99d06e1..0c964bd 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -594,8 +594,8 @@ explicitly written by software. The Interrupt bit in the {\tt scause} register is set if the trap was caused by an interrupt. The Exception Code field contains a code identifying the last exception. Table~\ref{scauses} -lists the possible exception codes for the current supervisor ISAs, in -descending order of priority. The Exception Code is a \wlrl\ field, +lists the possible exception codes for the current supervisor ISAs. +The Exception Code is a \wlrl\ field, so is only guaranteed to hold supported exception codes. \begin{figure*}[h!] @@ -657,7 +657,8 @@ so is only guaranteed to hold supported exception codes. \hline \end{tabular} \end{center} -\caption{Supervisor cause register ({\tt scause}) values after trap.} +\caption{Supervisor cause register ({\tt scause}) values after trap. +Synchronous exception priorities are given by Table~\ref{exception-priority}.} \label{scauses} \end{table*} |