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| author | Ved Shanbhogue <91900059+ved-rivos@users.noreply.github.com> | 2024-04-25 15:30:16 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-04-25 13:30:16 -0700 |
| commit | a9faf5790e0037942dc64004528af899773341fd (patch) | |
| tree | 7803a85018a2f07031bd24379391d15a1ddeecc2 | |
| parent | d306899b96db90722b7c5314e672d6691521daad (diff) | |
| download | riscv-isa-manual-a9faf5790e0037942dc64004528af899773341fd.zip riscv-isa-manual-a9faf5790e0037942dc64004528af899773341fd.tar.gz riscv-isa-manual-a9faf5790e0037942dc64004528af899773341fd.tar.bz2 | |
Update layout and fix broken citations (#1365)
| -rw-r--r-- | src/zacas.adoc | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/src/zacas.adoc b/src/zacas.adoc index b91b00b..1dd5231 100644 --- a/src/zacas.adoc +++ b/src/zacas.adoc @@ -1,7 +1,5 @@ == "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 -=== Introduction - Compare-and-Swap (CAS) provides an easy and typically faster way to perform thread synchronization operations when supported as a hardware instruction. CAS is typically used by lock-free and wait-free algorithms. This extension proposes @@ -20,12 +18,11 @@ quadword compare and swap (of both the pointer and the counter). The double and quadword CAS instructions support implementation of algorithms for ABA problem avoidance. -The Zacas extension depends upon the Zaamo extension cite:[unpriv]. +The Zacas extension depends upon the Zaamo extension. -[[chapter2]] -=== Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) +=== Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions -[wavedrom, , ] +[wavedrom, , svg] .... {reg: [ {bits: 7, name: 'opcode', attr:'AMO'}, @@ -67,6 +64,9 @@ pair is `x0`, then both halves of the pair read as zero. When the first register of a destination register pair is `x0`, then the entire register result is discarded and neither destination register is written. The operation performed by `AMOCAS.D` for RV32 is as follows: + +<<< + [listing] temp0 = mem[X(rs1)+0] temp1 = mem[X(rs1)+4] @@ -119,6 +119,9 @@ is `x0`, then both halves of the pair read as zero. When the first register of a destination register pair is `x0`, then the entire register result is discarded and neither destination register is written. The operation performed by `AMOCAS.Q` is as follows: + +<<< + [listing] temp0 = mem[X(rs1)+0] temp1 = mem[X(rs1)+8] @@ -196,8 +199,6 @@ not have release semantics, regardless of `rl`. An `AMOCAS.W/D/Q` instruction always requires write permissions. -<<< - [NOTE] ==== The following example code sequence illustrates the use of `AMOCAS.Q` to @@ -241,6 +242,8 @@ move_tail: # Tail was not pointing to the last node ==== +<<< + === Additional AMO PMAs There are four levels of PMA support defined for AMOs in the A extension. Zacas |