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author | Andrew Waterman <andrew@sifive.com> | 2019-04-15 15:05:44 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2019-04-15 15:07:22 -0700 |
commit | 8b6c812a0ac3d9c7117c535ca6a25d8094fc368f (patch) | |
tree | 27b617e621875a97518b4a37d14d4c866c24c44b | |
parent | ebac213077afc0f886b835304fd42819f7569cc5 (diff) | |
download | riscv-isa-manual-8b6c812a0ac3d9c7117c535ca6a25d8094fc368f.zip riscv-isa-manual-8b6c812a0ac3d9c7117c535ca6a25d8094fc368f.tar.gz riscv-isa-manual-8b6c812a0ac3d9c7117c535ca6a25d8094fc368f.tar.bz2 |
Update CSR access ordering section to clarify ordering is two-sided
This is just a clarification, as it follows from the accesses being
performed in program order.
-rw-r--r-- | src/csr.tex | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/src/csr.tex b/src/csr.tex index bb8f1aa..f309913 100644 --- a/src/csr.tex +++ b/src/csr.tex @@ -157,14 +157,16 @@ bits in the CSR when the old value is not required: CSRS/CSRC {\em \subsection*{CSR Access Ordering} -On a given hart, CSR accesses, including implicit CSR accesses, are performed -in program order with respect to those instructions whose execution behavior is -modified by the CSR accesses. In particular, a CSR read access returns the CSR -state after the execution of any prior instructions in program order that may -update the CSR state or whose execution behavior is modified by the CSR state, -and a CSR write updates the CSR state prior to the execution any subsequent -instructions in program order that consume the CSR state or whose execution -behavior is modified by the CSR state. +On a given hart, explicit and implicit CSR access are performed in program +order with respect to those instructions whose execution behavior is affected +by the state of the accessed CSR. In particular, a CSR access is performed +after the execution of any prior instructions in program order whose behavior +modifies or is modified by the CSR state and before the execution of any +subsequent instructions in program order whose behavior modifies or is modified +by the CSR state. Furthermore, a CSR read access instruction returns the +accessed CSR state before the execution of the instruction, while a CSR write +access instruction updates the accessed CSR state after the execution of the +instruction. Where the above program order does not hold, CSR accesses are weakly ordered, and the local hart or other harts may observe the CSR accesses in an order |