Update supervisor.adoc (#1382)riscv-isa-release-87edab7-2024-05-04

https://github.com/riscv/riscv-isa-manual/issues/1370

Signed-off-by: Kersten Richter <kersten@riscv.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/src/supervisor.adoc b/src/supervisor.adoc
index 6c2276d..5e33c4b 100644
--- a/src/supervisor.adoc
+++ b/src/supervisor.adoc
@@ -2186,14 +2186,14 @@ the trap handler commonly employs an `SRET` instruction to return from the trap.
 When Svvptc is implemented, the stores it executes to change the Valid bit
 of the PTEs from 0 to 1 then become visible to implicit references to those PTEs
 within a bounded timeframe. This visibility pertains to the instructions like
-the one causing the page-fault or those accessing new memory regions. A
+the one causing the page fault or those accessing new memory regions. A
 memory-management fence can be used to force immediate visibility of these PTE
 updates to all implicit references associated with instructions following the
 memory-management fence. However, when Svvptc is implemented, visibility (in a
 bounded amount of time) is guaranteed and use of a memory-management fence is
 not required in these scenarios. While this approach might lead to an occasional
 gratuitous page-fault, the performance benefit of omitting the memory-management
-fence instructions outweighs the occasional cost of a gratuitous page-fault.
+fence instructions outweighs the occasional cost of a gratuitous page fault.
 ====
 
 ////