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| author | wmat <wmat@riscv.org> | 2024-05-08 10:15:05 -0400 |
|---|---|---|
| committer | wmat <wmat@riscv.org> | 2024-05-08 10:15:05 -0400 |
| commit | 52382504bab08c2c0363fe1dfab8a91e514fc108 (patch) | |
| tree | 154941e71d63f132f27c505e5be6e4f301e102f4 | |
| parent | 8b77a726433a1ea8dfe9aa6c6313b43163990ade (diff) | |
| download | riscv-isa-manual-52382504bab08c2c0363fe1dfab8a91e514fc108.zip riscv-isa-manual-52382504bab08c2c0363fe1dfab8a91e514fc108.tar.gz riscv-isa-manual-52382504bab08c2c0363fe1dfab8a91e514fc108.tar.bz2 | |
Fixing sail inclusion.
Fixing sail inclusion.
| -rw-r--r-- | src/c-st-ext.adoc | 2 | ||||
| -rw-r--r-- | src/riscv-unprivileged.adoc | 2 | ||||
| -rw-r--r-- | src/rv64.adoc | 7 |
3 files changed, 6 insertions, 5 deletions
diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc index d99baeb..bd33ef9 100644 --- a/src/c-st-ext.adoc +++ b/src/c-st-ext.adoc @@ -310,7 +310,7 @@ only valid when _rd_≠x0 the code points with _rd_=x0 are reserved. C.LWSP SAIL Code: -sail::execute[clause="RISCV_C_LWSP(_, _)",part=body,unindent] +//include::sail:execute[part=body,unindent,clause="RISCV_C_LWSP(_, _)"] C.LDSP is an RV64C/RV128C-only instruction that loads a 64-bit value from memory into register _rd_. It computes its effective address by diff --git a/src/riscv-unprivileged.adoc b/src/riscv-unprivileged.adoc index a571d3c..e6b4145 100644 --- a/src/riscv-unprivileged.adoc +++ b/src/riscv-unprivileged.adoc @@ -52,7 +52,7 @@ endif::[] :approx: ≈ :inf: ∞ :csrname: envcfg -:sail_doc: ../src/sail-index/riscv_RV64.json +:sail-doc: ../src/sail-index/riscv_RV64.json _Contributors to all versions of the spec in alphabetical order (please contact editors to suggest corrections): Derek Atkins, diff --git a/src/rv64.adoc b/src/rv64.adoc index 26a864f..23af78e 100644 --- a/src/rv64.adoc +++ b/src/rv64.adoc @@ -52,7 +52,8 @@ register _rd_ (assembler pseudoinstruction SEXT.W). [source,sail] ---- -include::sail:execute[from=sail-rv64,part=body,dedent,clause="ADDIW(_,_,_)"] +include::sail:execute[part=body,dedent,clause="ADDIW(_,_,_)"] + ---- include::images/wavedrom/rv64i-slli.adoc[] @@ -72,7 +73,7 @@ copied into the vacated upper bits). (((RV64I, SRLIW))) (((RV64I, RV64I-only))) -sail::execute[from=sail-rv64,part=body,dedent,clause="SHIFTIOP(_,_,_,_)"] +include::sail:execute[part=body,dedent,clause="SHIFTIOP(_,_,_,_)"] include::images/wavedrom/rv64i-slliw.adoc[] [[rv64i-slliw]] @@ -82,7 +83,7 @@ defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. SLLIW, SRLIW, and SRAIW encodings with _imm[5] ≠ 0_ are reserved. -sail::execute[from=sail-rv64,part=body,dedent,clause="SHIFTW(_,_,_,_)"] +include::sail:execute[part=body,dedent,clause="ADDIW(_,_,_)"] [NOTE] |