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| author | Andrew Waterman <andrew@sifive.com> | 2024-04-24 10:25:57 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-04-24 10:26:12 -0700 |
| commit | 4a00e42f676bf2062ef3c54551804034f54c2c2f (patch) | |
| tree | 64ff6b0d909c97d668d382ebc8a64d018531ab99 | |
| parent | a6ecaa1e18f831de28c0c3afaeed224bb742e174 (diff) | |
| download | riscv-isa-manual-4a00e42f676bf2062ef3c54551804034f54c2c2f.zip riscv-isa-manual-4a00e42f676bf2062ef3c54551804034f54c2c2f.tar.gz riscv-isa-manual-4a00e42f676bf2062ef3c54551804034f54c2c2f.tar.bz2 | |
RNMI clarification
Needed because of 1153db082b34950dc282bc9b87727199c005c3ad
| -rw-r--r-- | src/rnmi.adoc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/rnmi.adoc b/src/rnmi.adoc index 9343976..aef8e9d 100644 --- a/src/rnmi.adoc +++ b/src/rnmi.adoc @@ -161,7 +161,7 @@ The RNMI handler can resume original execution using the new MNRET instruction, which restores the PC from `mnepc`, the privilege mode from `mnstatus`, and also sets `mnstatus`.NMIE, which re-enables interrupts. -If the hart encounters an exception while executing in M-mode with the `mnstatus`.NMIE bit clear, the actions taken are the same as if the exception had occurred while `mnstatus`.NMIE were set, except that the program counter is set to the RNMI exception trap handler address (rather than the address specified by `mtvec`). +If the hart encounters an exception while executing in M-mode with the `mnstatus`.NMIE bit clear, the actions taken are the same as if the exception had occurred while `mnstatus`.NMIE were set, except that the program counter is set to the RNMI exception trap handler address. [NOTE] ==== |