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| author | Scott Johnson <scottjohnsoninsf@gmail.com> | 2021-09-14 19:41:03 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-09-14 19:41:03 -0700 |
| commit | ce3beb8dccf645dd725e0bd495af160fbe56fa66 (patch) | |
| tree | af5ff3d296258127eb87bfd7f57e2de219d62ac1 | |
| parent | 0bb2e920c9795f62730d4c1ef1b36bd8e415a0f2 (diff) | |
| download | riscv-isa-manual-ce3beb8dccf645dd725e0bd495af160fbe56fa66.zip riscv-isa-manual-ce3beb8dccf645dd725e0bd495af160fbe56fa66.tar.gz riscv-isa-manual-ce3beb8dccf645dd725e0bd495af160fbe56fa66.tar.bz2 | |
Fix apparent typo re hpmcounter*h (#735)
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index eb8502a..ca8f7a1 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1770,7 +1770,7 @@ The {\tt cycle}, {\tt instret}, and {\tt hpmcounter{\em n}} CSRs are read-only shadows of {\tt mcycle}, {\tt minstret}, and {\tt mhpmcounter{\em n}}, respectively. The {\tt time} CSR is a read-only shadow of the memory-mapped {\tt mtime} register. Analogously, on RV32I the {\tt cycleh}, -{\tt instreth} and {\tt hpmcounter{\em n}} CSRs are read-only shadows of +{\tt instreth} and {\tt hpmcounter{\em n}h} CSRs are read-only shadows of {\tt mcycleh}, {\tt minstreth} and {\tt mhpmcounter{\em n}h}, respectively. On RV32I the {\tt timeh} CSR is a read-only shadow of the upper 32 bits of the memory-mapped {\tt mtime} register, while {\tt time} shadows only the |